Interpretation of transconductance dispersion in GaAs MESFET usingdeep level transient spectroscopy

The negative transconductance dispersion in a GaAs metal-semiconductor field-effect transistor (MESFET) was interpreted using both surface leakage current and capacitance deep level transient spectroscopy (DLTS) measurements. The transconductance of the device was reduced by 10% in the frequency range of 10 Hz ~1 kHz. The transition frequency shifted to higher frequency region with the increase of device temperature. The activation energy for the change of the transition frequency was determined to be 0.66±0.02 eV. It was found that the activation energy for the conductance of electrons on the surface of GaAs was 0.63±0.01 eV. In the DLTS spectra, two types of hole-like signals with activation energies, 0.65±0.07 eV (H1) and 0.88±0.04 eV (H2), were observed. The activation energy of H1 trap agrees well with those obtained from the transconductance dispersion and surface leakage current measurements. This demonstrates that surface state H1 causes the generation of surface leakage current, leading to the transconductance dispersion in the MESFET. Using the experimental results, a model for the evolution of hole-like signal by surface states in the capacitance DLTS is proposed     

The resonant-tunneling field-effect transistor: A new negative transconductance device

A new field-effect transistor with a resonant-tunneling barrier in the gate is presented. The gate and the drain currents versus gate voltage exhibit peaks when the resonant-tunneling gate current is quenched. Thus, in addition to negative differential resistance, this structure also exhibits negative transconductance, a unique feature in an n-channel device. Also, by proper gate bias, the same resonance of the double barrier can be used to produce two peaks in the drain current versus drain voltage characteristic at nearly the same current level. This is a very desirable feature for many applications.     

Two-dimensional device simulator for gate level characterization

A novel device simulator using a Newton-Raphson method for searching for the output terminal potential has been developed for composite structures with inverter function. We have found it impossible to determine the output potential and to characterize the transfer curve for such devices using conventional device simulators.The present simulator, however, can handle gate level device simulation, such as an inverter with a linear or a nonlinear load, and a CMOS inverter. Consequently, an inverter can be characterized exactly in steady and transient operation without circuit simulation. Thus device design with use of the present device simulator becomes more efficient. Specific examples are given to illustrate some comprehensive features of this simulator.     

A wafer-level approach to device lifetesting

An innovative wafer-level methodology is introduced and used to determine the thermal activation energies of TriQuint semiconductor’s TQPED devices. Activation energies of 2.77 eV and 2.44 eV are calculated for the depletion-mode and enhancement-mode devices, respectively. This accelerated lifetest technique utilizes a special reliability test structure that includes an on-wafer heating element around the device under test (DUT). The heating element easily achieved temperature above 275 °C without the need to bias the device. This allows the exclusive study of thermally activated failure mechanisms. The special reliability test structure allows the stressing of individual devices at different temperatures on the same wafer. This built-in flexibility allows for a fast and efficient means of evaluating device reliability by eliminating packaging overhead and considerations. In wafer form it becomes possible to spatially map the reliability of devices under test. It is also easier to observe the physical degradation of devices and determine the failure mechanisms.     

A novel finite-element approach to device modeling

A finite-element device-simulation program is presented. An adaptive grid-refinement procedure is used to minimize the number of nodes. Two different kinds of elements are generated (triangles and rectangles) thus enabling the use of an irregular mesh. Different shape functions have been developed for the three variables; they are linear/ bilinear for the electric potential and linear/bilinear in Bernoulli-like functions for the quasi-Fermi potentials. Numerical examples are presented.     

A generalized space-mapping tableau approach to device modeling

A comprehensive framework to engineering device modeling, which we call generalized space mapping (GSM) is introduced in this paper. GSM permits many different practical implementations. As a result, the accuracy of available empirical models of microwave devices can be significantly enhanced. We present three fundamental illustrations: a basic space-mapping super model (SMSM), frequency-space-mapping super model (FSMSM) and multiple space mapping (MSM). Two variations of MSM are presented: MSM for device responses and MSM for frequency intervals. We also present novel criteria to discriminate between coarse models of the same device. The SMSM, FSMSM, and MSM concepts have been verified on several modeling problems, typically utilizing a few relevant full-wave electromagnetic simulations. This paper presents four examples: a microstrip line, a microstrip right-angle bend, a microstrip step junction, and a microstrip shaped T-junction, yielding remarkable improvement within regions of interest     

A transconductance driven-right-leg circuit

Biopotential measurements are very sensitive to electromagnetic interference (EMI). EMI gets into the acquisition system by many ways, both as differential and common mode signals, driven-right-leg circuits (DRL) are widely used to reduce common mode interference. This paper reports an improvement on the classic DRL. The proposed circuit uses a transconductance amplifier to drive the patient's body. This configuration has some interesting properties, which provide an extended bandwidth for high-frequency EMI rejection (such as fluorescent lights interference). The improvement is around 20 dB for frequencies of few kilohertz and the circuit is easy to compensate for stability. A comparative analysis against a typical DRL is presented, the results obtained have been experimentally tested.     

Optoelectronic approach to on-chip device and circuit characterization at microwave and millimeter-wave frequencies

A practical technique for characterizing high-frequency semiconductor devices and monolithic integrated circuits has been developed, with specific emphasis on eliminating one of the primary concerns affiliated with conventional approaches, namely the often insufficient predictability of conditions at interfaces between measurement system and device under test. Arrays of high-speed photoconductive circuit elements, in conjunction with special compensation networks, are thereby utilized to implement, on chip, all signal generation and sampling functions needed to efficiently perform time-domain reflectometry. The acquired time-domain information is then converted into equivalent device-under-test scattering parameter responses. The practicability of the approach is experimentally demonstrated with the help of five individual test structures that are realized in monolithic-integrated-circuit format on a GaAs substrate and operate over a full, uninterrupted 100-GHz frequency interval.<>     

A novel approach to silicon gate CMOS device scaling

A new approach is reported for fabricating scaled Si-gate CMOS devices using medium temperature (?900° C) LPCVD deposited SiO₂ as the dielectric interlayer. The film can be deposited from 850 to 1000°C using a graded temperature profile and optimum pressure. A maximum of 100 wafers with 8% variation of thickness per run has been achieved using the process described in this paper. The medium-temperature LPCVD SiO₂ film exhibited step-coverage as good as the conventional low temperature PSG film. Since the new film requires no high temperature treatment, the convetional Si-gate CMOS diffusion process has been used to obtain the micron and submicron junction depths that are required to fabricate scaled CMOS devices. Such a processing approach, converting a 5–6 μm geometry CMOS process to a 3 μm geometry CMOS process, is described.     

Charge-coupled devices? A new approach to MIS device structures

Recent advances in materials and processing have resulted in a new class of information-handling structure?the charge-coupled device. This three-layer structure creates and stores minority carriers, or their absence, in potential wells near the surface of the semiconductor. The minority carriers move from under one electrode to a closely adjacent electrode on the same substrate when a more negative voltage is applied to the adjacent electrode. Because of their high transfer efficiency, these devices have already found application as image sensors. In addition, there is every expectation that memories made by use of the stored-charge concept will be less expensive and faster, and will require less power than a magnetic counterpart now in use.     

Lattice-gas approach to semiconductor device simulation

A new approach to semiconductor device simulation is presented which is based on a lattice-gas or cellular-automata model and is quite similar to methods recently explored in fluid dynamics. The approach obtains a stochastic solution to the diffusion-drift partial differential equations describing electron transport in semiconductors. The lattice-gas method appears to be fairly well-suited to electron transport simulation with its ability to handle complex geometry, its ease of programming and its stability being some key advantages. In addition, we show that the structure of the model itself—its Boolean character—leads to a partial inclusion of electron degeneracy effects. Finally, we make a preliminary assessment of the performance of the diffusion-drift lattice-gas model, finding it to be competitive with conventional approaches when its inherent parallelism is fully exploited.     

A new CMOS design of high transconductance current follower transconductance amplifier and its applications

In this work, a new CMOS implementation of high transconductance current follower transconductance amplifier (CFTA) is proposed. The proposed CFTA uses current starving technique along with an auxiliary unit (AU) to enhance transconductance performance. The cross-drain-coupled MOSFETs are also used in AU which further enhances transconductance of proposed circuit. The proposed CFTA provides higher transconductance and wider tuning range without affecting its output swing and bandwidth performance. The proposed CFTA provides transconductance of 11.3 mS, dissipates 1.8 mW power and operates at?±?0.6 V supply voltage. A current mode third order quadrature oscillator and biquad filter have been designed and simulated, to validate the performance of proposed circuit. The workability of proposed CFTA and its applications have been verified by using Cadence virtuoso schematic composer with TSMC 0.18 µm process parameters.     

Interface characterization of fully depleted SOI MOSFETs by thedynamic transconductance technique

The dynamic transconductance technique of MOSFET interface characterization is adapted to fully depleted silicon-on-insulator (SOI) transistors and is used to measure the interface-state density energy profiles in several SIMOX (separation by implanted oxygen) transistors. By making measurements first with the current flowing through the channel under measurement and then through the opposite channel, much of the energy gap (from accumulation to well into weak inversion) can be probed. Remarkably high sensitivity is achieved by utilizing the imaginary part of the dynamic transconductance. Measured interface trap densities were in the region of ~10¹⁰-10¹¹ eV^-1-cm^-2     

Analysis of capacitance and transconductance frequency dispersions in MESFETs for surface characterization

A theoretical model is developed for capacitance and transconductance frequency dispersion in MESFETs at low drain bias and is compared with experimental data obtained on commercial and special devices. It is shown that the results are consistent with a model in which the surface states have a density N_SS in the range of 10¹³ cm⁻² eV⁻¹ and are distributed over a depth of approximately 100 Å below the surface. It is found that a small N_SS contributes to an increase of the g_m dispersion and that the dispersion is minimized in recessed gate structures. Finally it is emphasized that g_m frequency measurements are very convenient for surface characterization and mostly for the evaluation of the spatial distribution of the interface traps when other techniques are inoperative.     

A novel fully differential telescopic operational transconductance amplifier

w rate are also enhanced.     

A high-voltage bipolar transconductance amplifier for electrotactile stimulation

This paper describes a high-performance transconductance amplifier specifically designed for electrotactile (electrocutaneous) stimulation. It enables voltages up to plusmn600 V to be produced at the output that will allow the psychophysiological performance associated with stimulation of the fingertip using various stimulation waveforms to be studied more thoroughly. The design has a transconductance of up to 20 mA/V, an 8.8-MOmega output resistance, and can provide output currents up to plusmn20 mA. A complete schematic diagram is presented along with a discussion of theory of operation and safety issues as well as performance and derating plots from the implemented design.     

Multi-frequency transconductance technique for interface characterization of deep sub-micron SOI–MOSFETs

A multi-frequency transconductance technique for interface characterization of sub-micron SOI–MOSFETs is implemented. This technique is shown to be highly suitable for interface characterization in SOI devices where conventional charge-pumping techniques cannot be applied. Using this multi-frequency technique, sub-micron SOI–MNSFETs with a SiN dielectric deposited by a novel jet-vapor-deposition (JVD) process are characterized. Results are compared with charge pumping results obtained on bulk MNSFETs with identically processed JVD nitrides.     

一种新的套筒式全差分跨导放大器设计

A novel fully differential telescopic operational transconductance amplifier （OTA） is proposed. An additional PMOS differential pair is introduced to improve the unit-gain bandwidth of the telescopic amplifier. At the same time, the slew rate is enhanced by the auxiliary slew rate boost circuits. The proposed OTA is designed in a 0.18 μm CMOS process. Simulation results show that there is a 49% improvement in the unit-gain bandwidth compared to that of a conventional OTA; moreover, the DC gain and the slew rate are also enhanced.