Negative-gate to substrate erase transient simulation for flash memory

We present a detailed and accurate physics based transient simulation for modeling flash memory erasing. Typical cells are erased by moving electrons from the floating gate to the drain, source or substrate. This paper addresses substrate erasing using a negative gate bias voltage based on the approximate solution to Poisson’s equation. Substrate erasing using a negative gate bias voltage is one of the more prevalent ways to erase flash memory in currently available consumer products. Many papers have been published on this topic but rarely present detailed derivations and none using this exact set of equations to model this erasing process.     

A simple and efficient self-limiting erase scheme for highperformance split-gate flash memory cells

This paper presents a fast self-limiting erase scheme for split-gate flash EEPROMs. In this technique the conventional erasing is rapidly followed by an efficient soft programming to correct for over-erase within the given voltage pulsewidth. The typical erasing time is about 400 ms and the final erased threshold voltage is accurately controlled via the base level read mode voltage within 0.3 V. The proposed scheme can he used for high throughput erasing in low voltage, high density, multilevel operation split-gate flash memory cells     

Lowering programmed voltage of organic memory transistors based on polymer gate electrets through heterojunction fabrication

The authors report on low operation voltage memory cells based on heterojunction ambipolar organic transistors with polymer gate electret (PGE). The introduction of the N,N′-dioctyl perylene diimide/pentacene heterojunction into the memory OFETs with PGE successfully lowered the memory cells’ reading, writing and erasing programmed voltages (reading voltage of 2 V, writing and erasing programmed voltages of 10 V). Meanwhile, the memory devices showed reproducible and durable memory behavior in more than 500 cycles’ testing. The built-in electric field-effect at heterojunction surface should efficiently reduce operation voltage of the memory devices.     

新型嵌入式BeNOR结构Flash存贮器

提出了一种能根据嵌入式应用系统容量的不同而灵活选择字节擦除和块擦除两种不同擦除模式的BeNOR阵列结构,该结构采用沟道热电子注入进行"写"操作,采用分离电压法负栅压源极F-N隧道效应进行擦除.对分离电压法负栅压源极F-N隧道效应擦除的研究表明,采用源极电压为5V,栅极电压为-10V的擦除条件,不仅能很好地控制擦除后的阈值电压,而且当字线宽度小于等于64时,源极电压导致的串扰效应能得到很好的抑制.研究表明该结构具有编程速度高、读取速度高、可靠性高及系统应用灵活的特点,非常适宜于在1M位以下的嵌入式系统中应用.     

20-Mb/s erase/record flash memory by asymmetrical operation

An asymmetrical recording and erasing operation of Flash memory is proposed where the threshold voltage of erase and record states are set above the thermal equilibrium threshold voltage. The recording rate is made ten times faster by using this method along with two other proposed methods: accurate control of the fastest bit and continuous recording using two memory banks. The erasing rate is also made ten times faster by using large-scale parallel operation made practical by a proposed multiphase word-driving scheme. These proposed circuit technologies will enable 20-Mb/s erase/record Flash memories for use in personal high-definition television (HDTV) movie cameras     

Characteristics of p-channel Si nano-crystal memory

In this work, the feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. By comparing the programming characteristics of devices with nano-crystals and devices without nano-crystals, the role of dots as storage node is presented. The programming and erasing mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. In case of erasing, the electron tunneling occurs from either the conduction band or the valence band. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time     

基于SiGe量子点实现增强F-N隧穿的低压闪速存储器

提出了一种用于半导体闪速存储器单元的新的Si/SiGe量子点/隧穿氧化层/多晶硅栅多层结构,该结构可以实现增强F-N隧穿的编程和擦除机制.模拟结果表明该结构具有高速和高可靠性的优点.测试结果表明该结构的工作电压比传统NAND结构的存储器单元降低了4V.采用该结构能够实现高速、低功耗和高可靠性的半导体闪速存储器.     

Low Voltage Flash Memory Cells Using SiGe Quantum Dots for Enhancing F-N Tunneling

提出了一种用于半导体闪速存储器单元的新的Si/SiGe量子点/隧穿氧化层/多晶硅栅多层结构,该结构可以实现增强F-N隧穿的编程和擦除机制.模拟结果表明该结构具有高速和高可靠性的优点.测试结果表明该结构的工作电压比传统NAND结构的存储器单元降低了4V.采用该结构能够实现高速、低功耗和高可靠性的半导体闪速存储器.     

A new multitime programmable non-volatile memory cell using high voltage NMOS

A new multitime programmable (MTP) non-volatile memory (NVM) cell using high voltage NMOS is proposed. A PMOS transistor is used for programming, erasing, and reading, and a high voltage NMOS is used for selecting the memory cell. The memory cell has fewer number of transistors and terminals compared with the typical conventional memory cell. This reduces the area consumption and simplifies the implementation of memory's external circuit. In addition, the subthreshold swing (SS) of the memory cell is improved for larger coupling ratio. Experimental investigation on transfer characteristics, endurance, retention, and threshold voltage V_TH shift and leakage current of the high voltage NMOS of the memory cell are presented. The experimental endurance behaviour of the proposed memory cell is superior to the conventional memory cell.     

一种改进的SOI Flash存储器

提出了一种缩短SOI Flash存储器浮栅长度的改进结构。对采用改进结构的器件进行仿真,结果表明,改进型结构与传统型结构相比,其存储窗口由3.7 V提升到4.9 V,提升了32%;在相同的阈值电压改变量(编程和擦除过程中阈值电压偏移量分别为3.5 V/-3.5 V)的情况下,所需的编程时间缩短了73%,擦除时间缩短了64%,表明改进型结构的性能得到了显著提高。     

利用改进的电荷泵法研究SONOS存储器陷阱电荷的分布特性

在silicon-oxide-nitride-oxide-silicon(SONOS)等电荷俘获型不挥发存储器中,编程操作后注入电荷的分布会对器件的读取、擦写以及可靠性带来影响.利用电荷泵方法可以有效而准确地测量出注入电荷沿沟道方向的分布.为了提高测试精度,在进行电荷泵测试时,采用固定低电平与固定高电平相结合的方法,分别对SONOS器件源端和漏端进行注入电荷分布的测试.通过测试,最终获得SONOS存储器在沟道热电子注入编程后的电子分布.电子分布的峰值区域在漏端附近,分布宽度在50nm左右.     

A self-convergence erase for NOR flash EEPROM using avalanche hotcarrier injection

A new erasing method for simple stacked gate NOR Flash EEPROM's is proposed and is applied to 2 M bit NOR Flash test array using 0.6 μm CMOS technology. Due to avalanche hot carrier injection after erasure by Fowler-Nordheim (F-N) tunneling current, the threshold voltages converge to a certain steady state. The steady state is a point of balance between the avalanche hot electron injection and the avalanche hot hole injection into the floating gate, and can be controlled easily by the channel doping and the applying control-gate voltage during convergence operation. The erasing method eliminates the problem of over-erased cells and realizes highly stable flash memory erasure     

Temperature dependant flash memory erase transient simulation (Part II)

We present a detailed and accurate physics based transient simulation for modeling flash memory erasing at ambient and non-ambient temperatures. Typical cells are erased by moving electrons from the floating gate to the drain, source or substrate. Part 1 of this paper derives the equations used to model substrate erasing. This paper addresses drain erase modeling using a simulation based on the solution to Poisson’s equation with temperature as an independent variable. The goal of this paper is to demonstrate the derivation of an accurate erase simulation and show the effects of temperature on the threshold voltage during the erase process. Several papers have been published on this topic but fail to present detailed derivations and none using this exact set of equations to model the temperature dependent erasing process.     

A 44-mm/sup 2/ four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller

The highest bit-density 64-Mb NOR flash memory with dual-operation function of 44 mm/sup 2/ was developed by introducing negative-gate channel-erase NOR flash memory cell technology, 0.16-/spl mu/m CMOS flash memory process technology, and four-bank hierarchical word-line and bit-line architecture. The chip has flexible block redundancy for high yield, a fast accurate word-line voltage controller for a fast erasing time of 0.5 s, and an eight-word page-read access capability for high read performance of an effective access time of 30 ns at a wide supply voltage range of 2.3-3.6 V.     

Successive charging/discharging of gate oxides in SOI MOSFET's bysequential hot-electron stressing of front/back channel

Hot-hole injection into the opposite channel of silicon-on-insulator (SOI) MOSFETs under hot-electron stress is reported. Sequential front/back-channel hot-electron stressing results in successive hot-electron/-hole injection, causing the threshold voltage to increase and decrease accordingly. This ability to inject hot holes into the opposite gate oxide can be used as an additional tool for studying the degradation mechanisms. Furthermore, it can be explored for possible use in designing SOI flash memory cells with back-channel-based erasing schemes     

Constant charge erasing scheme for flash memories

This paper presents a new erasing scheme for flash memories based on a sequence of bulk to gate-box pulses with increasing voltage amplitude. It is experimentally and analytically demonstrated that the erasing dynamics always reaches an equilibrium condition where each pulse induces a constant and controllable injected charge and, therefore, constant threshold shifts. The analytical study allows us to express both the final threshold voltage and the oxide electric field as a function of technological, physical, and electrical parameters. Electrical parameters can be conveniently adapted to control both the threshold voltage and the oxide fields, thus reducing oxide stresses. Advantages with respect to the standard box erasing scheme are theoretically and experimentally demonstrated     

Hi-MNOS II Technology for a 64-kbit Byte-Erasable 5-V-Only EEPROM

Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 /spl mu/m and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180/spl mu/m2, a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of /spl plusmn/1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 10/sup 4/ write/erase cycles.     

Temperature dependant flash memory erase transient simulation (Part I)

We present a detailed and accurate physics based transient simulation for modeling flash memory erasing at ambient and non-ambient temperatures. Typical cells are erased by moving electrons from the floating gate to the drain, source or substrate. Part I of this paper addresses substrate erase modeling using a simulation based on the solution to Poisson’s equation with temperature as an independent variable. The goal of this paper is to demonstrate the derivation of an accurate erase simulation and show the effects of temperature on the threshold voltage shift during the erase process. Several papers have been published on this topic but fail to present detailed derivations and none using this exact set of equations to model the temperature dependent erasing process.     

Narrow distribution of threshold Voltage in 4-Mbit MONOS memory-cell array with F-N channel write and direct/F-N tunneling erase operation as a single transistor structure

This paper describes the narrow and nonspreading distribution of threshold voltage in metal-oxide-nitride-oxide semiconductor (MONOS) memory cell array with Fowler-Nordheim (F-N) channel write operation and direct/F-N tunneling erase operation as a single transistor structure. We fabricated a 4-Mbit MONOS memory test chip using 0.25-/spl mu/m technology. The gate length of the memory cell was shrunk to 0.18 /spl mu/m. The distribution of threshold voltage for many operations were evaluated. The range of threshold voltage distribution is small, within 0.5 V in 12-14 V for programming and -8.5 to -9 V for erasing. It was also narrow for program/erase cycles up to 10/sup 4/ and after exposure to temperatures of 300/spl deg/C for 17 h and 150/spl deg/C for 304 h. These characteristics of narrow Vth distribution represent advantages of the MONOS memory device both for nonverify operation in program/erase mode and for low supply voltage operation in read mode. Another advantage is that no anomalous leak cell or tail bit is evident in the data retention result, demonstrating high reliability. The MONOS memory device is a promising candidate for use in cheaper and more scalable gate length fabrication processes compared with floating gate for highly reliable embedded applications.     

Hi-MNOS II technology for a 64-kbit byte-erasable 5-V-only EEPROM

Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 µm and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180 µm², a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of ± 1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 10⁴write/erase cycles.