一种基于复制码和汉明码的容错加法器

利用复制码(duplicated code)和汉明码(Hamming code)实现了一种新的容错加法器结构,对比之前提出的各种自检测(self-checking)加法器,该结构具有能在不需要重新计算的前提下,同时纠正出现在进位逻辑和求和逻辑上的软错误的特点.另一方面,该结构适用于各种利用基于行波进位的加法器结构,如旁路进位加法器、线性进位选择加法器和平方根进位选择加法器,并适合在汉明码校验的数据通路中工作.仿真结果表明,能有效地修正在进位逻辑上产生的多位软错误(soft error)和产生在求和逻辑上的单个软错误.     

一种基于GPU通用计算的容错方法

为确保GPU通用计算(GPGPU)程序在CPU-GPU异构平台上运行的可靠性,设计了一种以软件方法实现的容错模型.在分析GPGPU程序运行过程中瞬时故障的产生模式以及错误的传播路径后,对GPGPU程序运行所依赖的CPU端和GPU端分别进行容错设计,并针对GPGPU程序的运行特点,设计能够降低容错运算开销同时提升系统协同工作能力的优化方案,从而在提高GPGPU程序的可靠性的同时降低容错设计所带来的额外开销.通过对典型实例的测试验证了所提出的方案的可行性以及性能.     

一种防计算机病毒的容错方法

本文介绍了容错技术在反病毒方面的应用，首先描述容错反病毒的依据，面向容错的计算机病毒的刻划，然后阐述程序流监控器及其扩充的反病毒能力，最后叙述了ＮＶＰ对程序处理工具的保护。     

一种改进的频带复制方法

介绍了一种用于改进信源编码系统的新方法--频带复制(SBR).在保持相同感知音质的情况下,它可以大幅减小编码比特率.SBR是通过在编码端减小频谱带宽,在解码端复制相应的频谱来实现的.在此基础上,本文探讨了一种谱包络调整的改进方法.     

一种IP网络路由容错方法

IP网络路由容错是指网络在一个路由器发生故障不能工作时,另一个路由器自动接管失效的路由器,从而保证网络路由正常进行.介绍一种基于Cisco路由器的路由容错方法.     

一种IP网络路由容错方法

IP网络路由容错是指网络在一个路由器发生故障不能工作时 ,另一个路由器自动接管失效的路由器 ,从而保证网络路由正常进行。介绍一种基于Cisco路由器的路由容错方法     

一种IP网络路由容错方法

IP网络路由容错是指网络在一个路由器发生故障不能工作时,另一个路由器自动接管失效的路由器,从而保证网络路由正常进行.介绍一种基于Cisco路由器的路由容错方法.     

一种单向数据复制的实现方法

文章主要介绍了单向数据复制的方法.作者根据工作中的实际经验,提出了数据复制的一种方案.     

一种基于代理的拜占庭容错算法

针对目前拜占庭容错的分布式一致性算法对性能的影响,文中从算法过程出发,基于B-Raft算法,加入了代理(Proxy)机制,以此为优化点来提升因拜占庭容错而导致降低的效率,同时降低单点失效频率。实现代理(Proxy)机制的方法是在Leader节点选取之后,通过高斯混合模型(GMM)将Follower节点群分簇后分别选取代理节点(Proxy-Node,PB),通过Leader与PB的分层同步来均衡Leader节点的负载,提高一致化效率。     

一种单向数据复制的实现方法

文章主要介绍了单向数据复制的方法。作者根据工作中的实际经验，提出了数据复制的一种方案。     

化学气相沉积硫化锌中六方相形成机制及抑制方法分析

六方相ZnS由于光学上的各相异性而在不同晶相上具有不同的折射指数.立方相化学气相沉积硫化锌(CVDZnS)中的六方杂相加大了对入射光线的散射,严重影响材料本身的光学性能.通过不同实验条件下的对比,对促成立方相形成的机制进行了探讨和分析,证实了六方相的形成主要受沉积温度、沉积压力、Zn/H2S 3个沉积参数的影响.有针对性地提出了综合利用适当提高沉积温度、Zn/H2S和降低沉积压力等方式来抑制六方相生成的方法,制备出不含六方杂相且各向同性的CVDZnS.样品的红外透过率在近红外及中红外波段得到了改善.     

一种用于文本压缩的信源容错译码算法

LZ算法在文本压缩领域应用广泛。LZ译码以先前接收码字的译码结果形成字典,后续译码依赖于先前的重构数据,一旦压缩码字出现误码将会引起严重的误码扩散。分析了主流的LZ77算法编译码原理,讨论了输入误码对译码字典和解压数据的影响,研究了误码传播问题。在此基础上提出一种用于文本压缩数据的容错译码算法,指出容错处理对抑制误码传播及保证LZ77解压数据的完整性具有重要意义。     

一种能有效抑制窄带干扰的小波包多载波扩频系统

本文提出一种能有效抑制窄带干扰的基于小波包的多载波扩频接收系统.该系统通过小波包分析来自适应调整优化参数并进行抗干扰处理,使系统性能在高功率窄带干扰下得到改善.处理过程可与传统的基于小波包的多载波扩频系统解调解扩方式很好的相匹配,系统复杂度很低.研究与仿真结果表明,这种方案简单实用,具有良好的性能.在相同的处理条件下,性能要大大优于基于离散傅立叶变换(DFT)的多载波扩频系统.     

Analysis of a fault-tolerance scheme for processor ensembles

The authors analyze a locally redundant scheme (LR scheme) for designing fault-tolerant processor ensembles. A switching structure for reconfiguration is presented, and a detailed model for the yield analysis off the LR scheme that takes into account processor, switch, and link failures is developed. A negative binomial distribution is used for the yield statistics, as it best fits the empirical data. This model is used to compare the yields (with and without fault tolerance) of some architectural topologies. A dynamic analysis of the effect of residual redundancy on the improvement of operational system reliability is presented. The analysis reveals an appreciable improvement in the yield and operational system-reliability when the LR scheme is used. This analysis includes the reliability of switches and links, unlike previous analyses of fault-tolerant schemes. The empirical results show that ignoring switch reliability could result in an appreciable overestimate of system reliability     

High-speed on-chip ECC for synergistic fault-tolerance memory chips

The placement of error-correcting-code (ECC) systems on dynamic-RAM (DRAM) chips poses many practical problems, among which are increased access time and chip size. The authors describe an optimized, self-contained, and self-timed on-chip ECC system embedded in a high-speed 16-Mb DRAM chip. This chip also has redundant word and bit lines. The combination of redundancy and on-chip ECC produces a synergistic effect which results in a major increase in fault tolerance for the hard manufacturing defects. It also improves the reliability of the chip, regardless of manufacturing defects. This improvement is attained with only a 5-ns penalty in access time and an 11% increase in chip size     

One method for sample size evaluation

This paper presents an evaluation of sample size based on the beta distribution as an approximate distribution of relative frequency of defective item appearance in the sample. Three tables of numerical values of the sample size and one illustrative example are given.     

Exception handling and fault-tolerance in multimediasynchronization

This paper contributes toward exception handling and fault-tolerance in multimedia presentation. Our study is based on the well-known four phases in fault-tolerant computing: fault detection, damage assessment, error recovery, and continued service. We define a fault in multimedia synchronization and a simple fault detection mechanism. Using the concept of a partner set of a media stream, we assess the damage caused to media presentation due to a fault. From the point of error recovery and reducing synchronization failures, we introduce the ideas of a k-cycle virtual fault. A k-cycle virtual fault suggests the possibility of a failure in the future after k presentation cycles. Detection of a possible presentation failure in the future gives lead time to take corrective measures to avoid the failure. In order to handle exception conditions during a synchronization failure, we define pinned and sliding semantics of media presentation. These two semantics allow us to define different levels of quality of presentation during a failure. Finally, we present the detailed design of a fault-tolerant presentation architecture and prove its properties. We discuss how the ideas of virtual fault and damage assessment can be used in generating useful information for the underlying data transfer protocol so that synchronization failures can be reduced     

一种网络测试方法

网络已成为信息系统不可或缺的组成部分。网络的性能一定程度上决定了信息系统的性能。以对吞吐量的测试为例,结合实例描述了一种网络测试的方法,并对结果进行了分析。对网络其他的应用层面性能如延时和抖动等,都可以按该方法做少许改变。     

Nonplanar VLSI arrays with high fault-tolerance capabilities

VLSI architectures for improved fault tolerance are proposed and analyzed. The architectures include structures with two planar layers of processing elements as well as extended cubic designs. The analyses for arrays with various redundancy levels show remarkable improvement in both array yield and processor use over those exhibited conventional two-dimensional structures. This improvement can be attributed to the benefits of the third dimension to increase the flexibility in spares allocation. The architectures can readily substitute arrays based on mesh or four-nearest-neighbor interconnections. From the fault-tolerance viewpoint the cubic structures offer no appreciable performance improvement over the simpler two-layer structures