HEVC整数DCT变换与量化的FPGA实现

HEVC编码框架采用了比H.264/AVC面积更大的DCT变换和更为灵活的自适应量化,在提高数据处理速度的同时,降低了编解码的失真率.基于HEVC的变换量化原理和模块化的思想,采用并行流水线结构和无乘法器方案实现了整数DCT变换及量化部分.系统采用MODELSIM进行功能仿真,基于Altera公司的Cyclone Ⅱ系列可编程逻辑器件进行硬件验证测试,其最大时钟频率在170 MHz以上,数据处理能力在2 824 Mpixel/s以上,满足HEVC编码标准的性能要求,为HEVC编解码标准的硬件实现提供了参考.     

H.264中二进制算术编码的硬件实现

H.264标准中的二进制算术编码算法复杂,用软件实现起来速度慢,编码一个信号需要多个时钟周期。结合硬件实现特点,对算法流程进行合理优化,采用流水线设计方法,电路结构采用Verilog HDL进行RTL级描述,在Synplify平台上进行FPGA综合,介绍了H.264中二进制算术编码的FPGA实现方案。编码速度达到1 b/cycle,工作频率达到75.7 MHz,完全可以应用于视频图像的实时编码中。     

一种基于FPGA高性能H．264变换量化结构设计

H.264作为最新的视频编码标准具有很高的压缩性能,对它的研究具有重要的意义.根据H.264的变换量化算法设计一种基于FPGA的高性能变换量化处理结构,该结构采用流水线探作和分时复用技术,结果显示,该设计既节省了资源,又保证了效率;能够同时处理整个4×4块的全部16个残差输入数据,并在236个时钟内完成对1个宏块的残差数据从输入到反变换输出重建值的完整变换量化过程.它的处理速度和性能大大提高,可用于硬件加速.     

H.264中整数DCT变换及量化的DSP实现

在TI的TMS320DM642开发板上实现了H.264视频压缩编码标准中像素压缩模块的优化.重点对H.264协议中的整数DCT变换编码和量化进行了理论分析,并对其进行仿真及优化,有效地降低了整个模块的运行时钟数.实验结果表明该方法的优化取得了良好效果.     

H．264／AVC中量化的Verilog实现

视频压缩技术取得了日新月异的发展.运动图像专家组和视频编码专家组给出一种更好的视频压缩标准,确定为MPEG-4标准的第十部分,即H.264/AVC.H.264/AVC作为新一代视频压缩标准,具有超高压缩率.详细分析了H.264中量化算法,并用Verilog硬件描述语言编程实现量化功能,利用Modelsim进行仿真,得到正确的结果.分析了量化模块所消耗的硬件资源,提出用FPGA实现H.264量化的算法,使H.264能够用硬件的方法实现.     

H.264/AVC视频编码标准中CAVLC解码器的设计

提出了一种应用于H.264/AVC的快速低功耗CAVLC解码器设计方法.对较复杂的几个模块进行了算法和结构上的优化,减少了占用的硬件资源,降低了实现复杂性.仿真结果表明:采用该方法设计的解码器可以正确解码每个变换块中的变换系数,且能在一个时钟周期解出一个句法,完全可以满足H.264视频实时解码的要求.     

一种H.264/AVC反变换反量化IP核设计

提出了一种适用于H.264/AVC解码器功能完整的反变换反量化IP核的设计.设计中采用同一处理单元完成三种不同的反变换,反变换反量化的每个步骤采用独立的门控时钟控制,逻辑复用和门控时钟降低了功耗.实现结果表明本设计满足1080i高清码流的实时解码要求.     

H.264硬件解码核的FPGA实现

针对H.264/AVC的视频解码问题进行了研究,给出了H.264解码核的硬件实现方案,对熵解码CAVLC查表方案进行了优化.详细介绍了句法预测模块、反量化、逆DCT以及帧内预测模块的具体实现结构;并引入流水线、并行处理和状态机处理方法来提高处理速度,实现了解码结构上的优化.该算法在EP2S60F672C5ES FPGA上获得验证,结果表明给出的H.264解码算法是正确的,且有节省硬件资源和较快解码速度的优点.     

H.264指数哥伦布码解码部件的硬件设计和实现

提出了一种针对H.264视频编码标准的变长码-指数哥伦布码解码的硬件设计结构,对传统的桶形移位器进行优化,主要采用基于PLA的并行解码算法以达到实时解码,同时辅助使用串行解码算法降低硬件资源消耗,保证在能够对符合H.264标准baseline Profile的码流实时解码的基础上优化了电路资源,给出实现该硬件结构对应的FPGA仿真结果及其ASIC硬件规模.     

H.264解码器FPGA实现中的USB下载接口设计

本文介绍了如何利用USB接口为H.264解码器FPGA验证平台提供文件下载功能,并根据H.264解码器的特点分别从硬件设计、FPGA固件设计、USB驱动程序设计和USB应用程序设计四个方面对该系统的结构和功能进行了阐述.     

A structured fixed-rate vector quantizer derived from avariable-length scalar quantizer. II. Vector sources

For Pt.I see ibid., vol.39, no.3, p.851-67 (1993). The fixed-rate scalar-vector quantizer (SVQ) for quantizing stationary memoryless sources is extended to a specific type of vector source in which each component is a stationary memoryless scalar subsource independent of the other components. Algorithms for the design and implementation of the original SVQ are modified to apply to this case. The resulting SVQ, referred to as the extended SVQ (ESVQ), is then used to quantize stationary sources with memory (with known autocorrelation function). Numerical results are presented for the quantization of first-order Gauss-Markov sources using this scheme. It is shown that the ESVQ-based scheme performs very close to entropy-coded transform quantization while maintaining a fixed-rate output and outperforms the fixed-rate scheme that uses scalar Lloyd-Max quantization of the transform coefficients. It is also shown that this scheme performs better than implementable vector quantizers, especially at high rates     

The quantized DCT and its application to DCT-based video coding

The two-dimensional (2-D) discrete cosine transform (DCT) and the subsequent quantization of the transform coefficients are two computationally demanding steps of any DCT-based video encoder. In this paper, we propose an efficient joint implementation of these two steps, where the precision in computing the DCT can be exchanged for a reduction in the computational complexity. First, the quantization is embedded in the DCT, thus eliminating the need to explicitly quantize the transform coefficients. A multiplierless integer implementation of the quantized DCT (QDCT) is then proposed that performs shift and add operations instead of full multiplications. A sequence of multiplierless QDCT algorithms is obtained with increasing precision and number of computations. Finally, further savings in computations are obtained by terminating the DCT computations whenever intermediate results indicate that the transform and quantization steps will likely result in a block of zero values. The proposed algorithms are applied to, and results are presented for, high-quality MPEG-2 and low bit rate H.263 video encoding.     

An Integrated Systolic Array Design for Video Compression

This paper presents an integrated systolic array design for implementing full-search block matching, 2-D discrete wavelet transform, and full-search vector quantization on the same VLSI architecture. These functions are the prime components in video compression and take a great amount of computation. To meet the real-time application requirements, many systolic array architectures are proposed for individually performing one of those functions. However, these functions contain similar computational procedure. The matrix-vector product forms of the three functions are quite analogous. After extracting the common computation component, we design an integrated one-dimensional systolic array that can perform aforementioned three functions. The proposed architecture can efficiently perform three typical functions: (1) the full-search block matching with block of size 16 × 16 and the search are from –8 to 7; (2) the 2-D 2 level Harr transform with block of size 8 × 8; and (3) the full-search vector quantization with input vector of size 2 × 2. A utilization rate of 100% to 97% is achieved in the course of executing full-search block matching and full-search vector quantization. When it comes to perform 2-D discrete wavelet transform, the utilization rate is about 32%. The proposed integrated architecture has lowered hardware cost and reduced hardware structure. It befits the VLSI implementation for video/image compression applications.     

AVS编码变换量化和扫描硬件设计与实现

本文提出了满足AVS实时高清视频编码的变换、量化、反量化、反变换和扫描的硬件设计方案.该设计方案以宏块为单位进行操作,通过采用乒乓操作和流水线技术,提供了高性能的并行数据处理能力.本文根据AVS变换和反变换的特点,设计了RAM行列存储器,实现高速并行转置,同时,提出了利用RAM实现并行扫描的方法及其结构,提供高数据吞吐...     

Canonical coordinates for transform coding of noisy sources

Based on the additive white quantization noise model, linear transform coders are derived for Gaussian sources corrupted by noise. There are two alternative design objectives: minimizing the trace of the error correlation matrix and thus minimizing the mean-squared error, or minimizing the determinant of the error correlation matrix and thus maximizing information rate. It is shown that a solution to both problems is to first transform the noisy observations into canonical coordinates, quantize and apply a Wiener filter in this coordinate system, and then transform the result back to the original coordinates. Canonical coordinates are uncorrelated, and quantization and Wiener filtering are applied to each component independently. The type of canonical coordinate system depends on the design objective: Quantization in half-canonical coordinates minimizes the mean-squared error and quantization in full-canonical coordinates maximizes information rate. Finally, it is also demonstrated in this paper that majorization is the fundamental principle underlying proofs of optimal transform coding.     

Progressive coding and transmission of digital diagnostic pictures

In radiology, as a result of the increased utilization of digital imaging modalities, such as computed tomography (CT) and magnetic resonance imaging (MRI), over a third of the images produced in a typical radiology department are currently in digital form, and this percentage is steadily increasing. Image compression provides a means for the economical storage and efficient transmission of these diagnostic pictures. The level of coding distortion that can be accepted for clinical diagnosis purposes is not yet well-defined. In this paper we introduce some constraints on the design of existing transform codes in order to achieve progressive image transmission efficiently. The design constraints allow the image quality to be asymptotically improved such that the proper clinical diagnoses are always possible. The modified transform code outperforms simple spatial-domain codes by providing higher quality of the intermediately reconstructed images. The improvement is 10 dB for a compression factor of 256:1, and it is as high as 17.5 dB for a factor of 8:1. A novel progressive quantization scheme is developed for optimal progressive transmission of transformed diagnostic images. Combined with a discrete cosine transform, the new approach delivers intermediately reconstructed images of comparable quality twice as fast as the more usual zig-zag sampled approach. The quantization procedure is suitable for hardware implementation.     

一维DCT变换编码的有限字长效应分析

本文对一维DCT变换压缩编码中变换域系数二次量化引起的图象损伤进行了频域和空间域分析，得出了一些有用的结论．通过对变换矩阵系数字长的分析和计算机模拟，为一维DCT变换压缩编码硬件实现时字长的确定提供了依据．硬件实验结果印证了上述分析的结论．