共查询到18条相似文献,搜索用时 140 毫秒
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幅频算术对称无源带通滤波器的优化设计 总被引:1,自引:3,他引:1
为解决无源带通滤波器幅频算术对称问题,提出一种基于极点放置技术的优化设计方法,即在网络综合法设计的滤波器电路基础上,将并臂电感换成串臂电感,在此电感上并联电容增加衰减极点,并利用电路优化技术,使得幅频特性算术对称.实例结果表明,该方法能够使滤波器幅频特性算术对称,而且带内波动小,电路结构简单,阶数少,插入损耗低. 相似文献
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群时延内均衡的模拟滤波器优化设计 总被引:1,自引:1,他引:0
为解决滤波器幅频特性算术对称性和通带内群时延波动之间的矛盾,提出了一种滤波器群时延内均衡优化设计方法,即在网络综合法设计的滤波器电路基础上,将电路与时延均衡器直接耦合,用最小二乘法使群时延特性逼近一个常数,然后利用无约束优化算法对整个电路进行优化来降低通带内群时延波动.仿真结果表明,该方法不但能使滤波器幅频特性算术对称... 相似文献
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针对网络综合方法不能直接设计滤波器驻波比的问题,提出了一种改进电路的滤波器驻波比优化设计方法,即在网络综合法设计滤波电路的基础上,把电路输入输出端的并臂电感转换为串臂电感,并直接并联电容以增加衰减极点,然后利用电路优化技术使得幅频特性对称且通带内驻波比接近于1.仿真结果表明,优化后UHF频段超带宽滤波器幅频特性接近算术... 相似文献
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介绍了一种交叉耦合微波滤波器的自适应顸失真理论。该理论在传统预失真理论的基础上,实现了传输极点向如轴的异步移动。每一个极点移动的距离,可以通过最小二乘法优化得到,避免了传统预失真中极点同步移动的盲目性。虽然传统预失真技术可以使滤波器通带内损耗变化及群时延变得较为平坦,但这是以增大插入损耗、回波损耗为代价的。采用自适应预失真技术,滤波器的电参数将得到较好的折衷。同时,通过选择合适的反射零点,可以综合出物理结构对称或者同步调谐滤波器对应的耦合矩阵。 相似文献
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本文介绍了电视差转机用声表面波滤波器(SAWF)的设计及其性能.测量了其幅频特性和群时延特性,并利用2T脉冲、条线号、250kHz方波进行了直接验证.装有这种SAWF的差转机已在我国投入应用. 相似文献
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推挽DC-DC变换器建模与控制设计 总被引:1,自引:0,他引:1
运用状态空间平均法,推导出连续导电模式下非理想电压型推挽DC-DC变换器功率级电路的低频小信号传递函数,仿真出变换器功率级电路的幅频和相频曲线(Bode图),通过优化设计反馈补偿电路,可以提高电压型推挽DC-DC变换器系统的稳定性和动态特性。对一台电压型推挽DC-DC变换器样机进行仿真和控制设计,应用网络分析仪Agilent4395A分别测试功率级电路和变换器系统的Bode图,并应用示波器测试变换器系统的负载动态响应,验证了建模和控制设计的正确性。 相似文献
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基于Matlab的模拟滤波器设计与仿真 总被引:1,自引:0,他引:1
巴特沃思、切比雪夫模拟低通滤波器通常是设计模拟高通、带通和带阻滤波器的原型,先按给定频率响应巴特沃思、切比雪夫低通Ha(s)逼近,然后由选定Ha(s)实现二端口网络的电路结构和参数值。在此对达林顿T型和П型电路结构的滤波器元件参数进行了编程计算,并对其系统函数的幅频特性进行仿真。仿真结果符合设计要求,该方法便捷,程序具有可扩展性。 相似文献
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通过Multisim 10.1软件对静态工作点稳定电路的频率响应进行了仿真,观察到了放大电路幅频特性波特图的变化规律,采用波特仪分析了耦合电容或旁路电容的大小变化引起下限截止频率的变化和发射极电阻的变化引起上限截止频率的变化,得出了虚拟仿真结果与实际理论计算相吻合。通过实例验证了,将Multisim 10.1仿真软件合理地引入电子电路实践教学后,可使电子电路理论教学变得更具体,有利于电子电路课程的教学质量提高。 相似文献
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《Microwave Theory and Techniques》1984,32(1):51-57
The properties of the mismatched symmetrical five-port circuit are discussed, i.e., the equations for the maximum and minimum couplings of a mismatched symmetrical five-port circuit are derived by appropriate approximations. The approximate equations for the maximum and minimum phase differences due to mismatches of a symmetrical five-port circuit are also derived. Furthermore, a broad-band design theory of a symmetrical five-port circuit with microstrip line is propsed by applying a matching technique which adds a generalized compensating network and matching sections to the fundamental symmetrical five-port circuit. Thus, the bandwidth of the proposed broad-band symmetrical five-port circuit extends to about an octave. The experimental verification has been achieved, and, hence, the validity of the design method is confirmed. 相似文献
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An optimization based approach to the design of E-plane filters is described. An optimization procedure based on Cohn's equal ripple optimization is developed. This vector procedure has several advantages over the general purpose optimization routines previously applied to the design of F-plane filters. The problem of local minima does not arise. Optimization is carried out with respect to the Chebyshev (or minimax) criteria. Less frequency sampling and therefore less calculation of the electrical parameters of E-plane discontinuities is required. The design of a symmetrical F-plane filter is considered. Higher order mode interaction between E-plane discontinuities is not included in the design. For the design example considered this is shown not to be significant. A numerically efficient method, requiring only real scalar arithmetic, for calculating the insertion loss of a symmetrical cascade of lossless symmetrical 2-ports is employed. Measurements on a fabricated filter confirm the accuracy of the design procedure 相似文献
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Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination
A design technique based on a combination of Common Sub-Expression Elimination and Bit-Slice (CSE-BitSlice) arithmetic for
hardware and performance optimization of multiplier designs with variable operands is presented in this paper. The CSE-BitSlice
technique can be extended to hardware optimization of multiplier circuits operating on vectors or matrices of variables. The
CSE-BitSlice technique has been applied to the design and implementation of 12 × 12 and 42 × 42 bit real multipliers, a complex
multiplier, a 6-tap FIR filter, and a 5-point DFT circuit. For comparison purposes, circuit implementations of the same arithmetic
and DSP functions have been carried out using Radix-4 Booth and CSA algorithms. Simulation results based on implementations
using the Xilinx FPGA 5VLX330FF1760-2 device shows that the circuits based on the CSE-BitSlice techniques require fewer logic
resources and yield higher throughput as compared to the CSA and Radix-4 Booth based circuits. 相似文献