共查询到19条相似文献,搜索用时 125 毫秒
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基于AVS标准的熵解码器硬件设计 总被引:1,自引:1,他引:0
提出了一种基于AVS标准熵解码器的设计方案.采用桶形移位器进行移位,采用并行结构确定码长.采用算术方法对19张码表进行算术优化,从而减小了芯片面积,提高了解码速度.采用Verilog HDL语言进行源代码设计和仿真.在0.25 μmCMOS工艺库下,用Design Compiler进行综合,面积为1.5万门左右,最高频率达100 MHz,达到实时解码高清AVS码流要求. 相似文献
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通过对LDPC码解码算法及解码器结构的研究,本文提出一种改进型高吞吐率QC-LDPC码解码器设计方案.综合考虑硬件复杂度和解码吞吐率,该方案利用分层解码算法和部分并行结构进行设计,并采用提前检测技术,消除冗余的迭代,实现高吞吐率.然后通过ModelSim SE6.0对该解码器进行仿真测试,验证了其功能的正确性,最后采用... 相似文献
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适用于AVS的自适应环路滤波器硬件设计 总被引:2,自引:0,他引:2
设计了一种适合于AVS的自适应环路滤波器,由于计算复杂度高的特点,采用并行加流水的方法实现自适应环路滤波的硬件设计,达到了实时解码的要求.采用Verilog语言进行设计、仿真,通过FPGA验证.用0.18μmCMOS工艺库综合,电路规模为3万门左右,最高频率能够达到140MHz,可实时解码720p/1080i高清AVS码流. 相似文献
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本文设计了一种适用于H.264标准的Exp-Golomb硬件解码器,通过在电路设计中采用桶形移位器、首一检测器等关键单元,实现了码长的快速检测和码流的连续处理,单个时钟周期内可解一个句法元素,有效减少了硬件资源的损耗。 相似文献
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本文主要介绍了AVS视频解码的关键技术及解码原理。针对AVS视频解码器开源代码RM52J_r1解码效率相对低下的问题,根据该开源代码设计了新的AVS解码器。实验结果表明,在保证解码质量的前提下,解码速度有了很大的提高,基本上能达到实时解码的要求。 相似文献
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AVS中可变长解码器的硬件设计 总被引:1,自引:0,他引:1
AVS是我国自主制定的音视频编码技术标准。简要介绍AVS标准视频压缩部分的特点,重点研究AVS可变长熵解码的原理和技术方法并进行优化,主要采用并行解码结构以达到实时解码。在此基础上提出了一种针对AVS视频编码标准的变长码——指数哥伦布码解码的硬件设计结构,最后给出实现该硬件结构对应FPGA实验仿真结果。 相似文献
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根据AVS标准中帧内预测的算法,运用流水线设计方法,并合理安排缓冲存储器空间,利用FPGA实现了帧内预测系统;然后将该设计的ModelSim仿真结果与参考软件的解码输出进行了比较,结果表明本设计能够较好地完成帧内解码算法,方便地嵌入到整体AVS解码系统中。 相似文献
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AVS编解码器采用环路滤波去除块效应来提高图像质量,而环路滤波复杂度高、运算量大,且滤波过程数据访问频繁,严重影响了代码的执行效率.为提高解码速率,通过分析滤波算法特点,调整滤波结构,优化滤波算法,部分代码采用DSP汇编语言.结果表明与传统的C相比,缩短了代码运行时间,提高了执行速度,达到实时解码的要求. 相似文献
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An architecture of entropy decoder,inverse quantiser and predictor for multi-standard video decoding
Leibo Liu Yingjie Chen Shouyi Yin Hao Lei Guanghui He Shaojun Wei 《International Journal of Electronics》2013,100(7):877-893
A VLSI architecture for entropy decoder, inverse quantiser and predictor is proposed in this article. This architecture is used for decoding video streams of three standards on a single chip, i.e. H.264/AVC, AVS (China National Audio Video coding Standard) and MPEG2. The proposed scheme is called MPMP (Macro-block-Parallel based Multilevel Pipeline), which is intended to improve the decoding performance to satisfy the real-time requirements while maintaining a reasonable area and power consumption. Several techniques, such as slice level pipeline, MB (Macro-Block) level pipeline, MB level parallel, etc., are adopted. Input and output buffers for the inverse quantiser and predictor are shared by the decoding engines for H.264, AVS and MPEG2, therefore effectively reducing the implementation overhead. Simulation shows that decoding process consumes 512, 435 and 438 clock cycles per MB in H.264, AVS and MPEG2, respectively. Owing to the proposed techniques, the video decoder can support H.264 HP (High Profile) 1920 × 1088@30fps (frame per second) streams, AVS JP (Jizhun Profile) 1920 × 1088@41fps streams and MPEG2 MP (Main Profile) 1920 × 1088@39fps streams when exploiting a 200 MHz working frequency. 相似文献
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《Signal Processing: Image Communication》2009,24(4):312-323
AVS1-P2 is the newest video standard of Audio Video coding Standard (AVS) workgroup of China, which provides close performance to H.264/AVC main profile with lower complexity. In this paper, a platform-independent software package with macroblock-based (MB-based) architecture is proposed to facilitate AVS video standard implementation on embedded system. Compared with the frame-based architecture, which is commonly utilized for PC platform oriented video applications, the MB-based decoder performs all of the decoding processes, except the high-level syntax parsing, in a set of MB-based buffers with adequate size for saving the information of the current MB and the neighboring reference MBs to minimize the on-chip memory and to save the time consumed in on-chip/off-chip data transfer. By modifying the data flow and decoding hierarchy, simulating the data transfer between the on-chip memory and the off-chip memory, and modularizing the buffer definition and management for low-level decoding kernels, the MB-based system architecture provides over 80% reduction in on-chip memory compared to the frame-based architecture when decoding 720p sequences. The storage complexity is also analyzed by referencing the performance evaluation of the MB-based decoder. The MB-based decoder implementation provides an efficient reference to facilitate development of AVS applications on embedded system. The complexity analysis provides rough storage complexity requirements for AVS video standard implementation and optimization. 相似文献
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AVS游程解码、反扫描、反量化和反变换优化设计 总被引:5,自引:0,他引:5
提出了一种适用于AVS的游程解码、反扫描、反量化和反变换硬件结构优化设计方案。根据AVS整数变换和量化的特性,设计了可工作在不同模式的存储器阵列,既可用来进行反变换器所需的转置操作,又可用来存储中间结果,将游程解码、反扫描和反量化合并为一个流水线单元并行处理。该设计省去了存储中间结果所需的大量存储器,加快了处理速度,满足高清视频的处理要求。该设计通过了FPGA验证,综合结果表明,其逻辑门数仅为9076,最高工作频率大于200MHz。 相似文献