A 1.5-V differential cross-coupled bootstrapped BiCMOS logic forlow-voltage applications

Two new bipolar complementary metal-oxide-semiconductor (BiCMOS) differential logic circuits called differential cross-coupled bootstrapped BiCMOS (DC²B-BiCMOS) and differential cross-coupled BiCMOS (DC²-BiCMOS) logic are proposed and analyzed. In the proposed two new logic circuits, the novel cross-coupled BiCMOS buffer circuit structure is used to achieve high-speed operation under low supply voltage. Moreover, a new bootstrapping technique that uses only one bootstrapping capacitor is adopted in the proposed DC²B-BiCMOS logic to achieve fast near-full-swing operation at 1.5 V supply voltage for two differential outputs. HSPICE simulation results have shown that the new DC²B-BiCMOS at 1.5 V and the new DC²-BiCMOS logic at 2 V have better speed performance than that of CMOS and other BiCMOS differential logic gates. It has been verified by the measurement results on an experimental chip of three-input DC²B-BiCMOS XOR/XNOR gate chain fabricated by 0.8 μm BiCMOS technology that the speed of DC²-BiCMOS at 1.5 V is about 1.8 times of that of the CMOS logic at 1.5 V. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed DC²B-BiCMOS and DC²-BiCMOS logic circuits are feasible for low-voltage, high-speed applications     

A delay model and optimization method of a low-power BiCMOS logiccircuit

A new delay model and optimization method is proposed for a low-power BiCMOS driver. A transient overdrive, base directly-tied complementary BiCMOS logic circuit operates faster than conventional BiCMOS and CMOS circuits for supply voltage down to 1.5 V by using a speed-power-area optimization approach. An analytical delay expression is derived for the first time for a full-swing BiCMOS circuit with short-channel effects. The circuit is simulated with a HSPICE model using 0.8-μm BiCMOS technology with a 6-GHz n-p-n and a 1-GHz p-n-p transistor. The simulation results have verified the analytical results and demonstrated that the circuit can work up to 200 MHz operating frequency for a load capacitance of 1 pF at 1.5 V of supply voltage     

Bootstrapped full-swing BiCMOS/BiNMOS logic circuits for 1.2-3.3 Vsupply voltage regime

Novel full-swing BiCMOS/BiNMOS logic circuits using bootstrapping in the pull-up section for low supply voltage down to 1 V are reported. These circuit configurations use noncomplementary BiCMOS technology. Simulations have shown that they outperform other BiCMOS circuits at low supply voltage using 0.35 μm BiCMOS process. The delay and power dissipation of several NAND configurations have been compared. The new circuits offer delay reduction between 40 and 66% over CMOS in the range 1.2-3.3 V supply voltage. The minimum fanout at which the new circuits outperform CMOS gate is 5, which is lower than that of other gates particularly for sub-2.5 V operation     

A 1.5-V full-swing BiCMOS logic circuit

A BiCMOS logic circuit applicable to sub-2-V digital circuits has been developed. A transiently saturated full-swing BiCMOS (TS-FS-BiCMOS) logic circuit operates twice as fast as CMOS at 1.5-V supply. A newly developed transient-saturation technique, with which bipolar transistors saturate only during switching periods, is the key to sub-2-V operation because a high-speed full-swing operation is achieved to remove the voltage loss due to the base-emitter turn-on voltage. Both small load dependence and small fan-in dependence of gate delay time are attained with this technique. A two-input gate fabricated with 0.3-μm BiCMOS technology verifies the performance advantage of TS-FS-BiCMOS over other BiCMOS circuits and CMOS at sub 2-V supply     

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump

A BiCMOS logic circuit with very small input capacitance has been developed, which operates at low supply voltages. A High-beta BiCMOS (Hβ-BiCMOS) gate circuit which fully utilizes the bipolar transistor features achieves 10 times the speed of a CMOS gate circuit with the same input capacitance and operating at 3.3 V supply voltage. In order to lower the minimum supply voltage of Hβ-BiCMOS, a BiCMOS circuit configuration using a charge pump to pull up the output high level of the BiCMOS gate circuit is proposed. By introducing a BiCMOS charge pump, Hβ-BiCMOS achieves very high speed operation at sub-2.0 V supply voltage. It has also been demonstrated that only a very small number of charge pump circuits are required to drive a large number of Hβ-BiCMOS gate circuits     

Study of BiCMOS logic gate configurations for improved low-voltageperformance

A simple BiCMOS configuration employing the source-well tie PMOS/n-p-n pull-down combination is proposed for low-voltage, high-performance operations. The improved BiCMOS gate delay time over that of the NMOS/n-p-n (conventional) BiCMOS gate is confirmed by means of inverter simulations and measured ring oscillator data. The source-well tie PMOS/n-p-n BiCMOS gate outperforms its conventional BiCMOS counterpart in the low-voltage supply range, at both high and low temperatures. A critical speed path from the 68030 internal circuit is used as a benchmark for the proposed BiCMOS design technique. The measured propagation delay of the BiCMOS speed path is faster than its CMOS counterpart down to 2.3 V supply voltage at -10°C and sub-2 V at 110°C     

A BiCMOS wired-OR logic

This paper proposes a BiCMOS wired-OR logic for high-speed multiple input logic gates. The logic utilizes the bipolar wired-OR to circumvent the use of a series connection of MOS transistors. The BiCMOS wired-OR logic was found to be the fastest compared with such conventional gates as CMOS NOR, BiCMOS multiemitter logic and CMOS wired-NOR logic, when the number of inputs was more than four and the supply voltage was 3.3 V. The BiCMOS wired-OR logic was also determined to be the fastest of the four when the fan-out number was below 20 and the number of inputs was eight. In addition, the speed was more than twice as faster when the fan-out number was less than 10. The BiCMOS wired-OR logic was applied to a 64-b 2-stage carry look-ahead adder, and was fabricated with a 0.5-μm BiCMOS process technology. A critical path delay time of 3.1 ns from an input to a sum output was obtained at the supply voltage of 3.3 V. This is 35% faster than that of conventional BiCMOS adders     

Full-swing Schottky BiCMOS/BiNMOS and the effects of operatingfrequency and supply voltage scaling

Novel full-swing BiCMOS/BiNMOS logic circuits which use Schottky diode in the pull-up section for low supply-voltage regime are developed. The full-swing pull-up operation is performed by saturating the bipolar transistor with a base current pulse. After which, the base is isolated and bootstrapped to a voltage higher than V_DD. The BiCMOS/BiNMOS circuits do not require a PNP bipolar transistor. They outperform other BiCMOS circuits at low supply voltage, particularly at 2 V using 0.5 μm BiCMOS technology. Delay, area, and power dissipation comparisons have been performed. The new circuits offer delay reduction at 2 V supply voltage of 37% to 56% over CMOS. The minimum fanout at which the new circuits outperform CMOS gate is 2 to 3. Furthermore, the effect of the operating frequency on the delay of a wide range of BiCMOS and BiNMOS circuits is reported for the first time, showing the superiority of the Schottky circuits     

0.5-μm 3.3-V BiCMOS standard cells with 32-kilobyte cache andten-port register file

BiCMOS standard cell macros, including a 0.5-W 3-ns register file, a 0.6-W 5-ns 32-kbyte cache, a 0.2-W 3-ns table look-aside buffer (TLB), and a 0.1-W 3-ns adder, are designed with a 0.5-μm BiCMOS technology. A supply voltage of 3.3 V is used to achieve low power consumption. Several BiCMOS/CMOS circuits, such as a self-aligned threshold inverter (SATI) sense amplifier and an ECL HIT logic are used to realize high-speed operation at the low supply voltage. The performance of the BiCMOS macros is verified using a fabricated test chip     

A new true-single-phase-clocking BiCMOS dynamic pipelined logicfamily for high-speed, low-voltage pipelined system applications

New true-single-phase-clocking (TSPC) BiCMOS/BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications are simulated by using HSPICE with 1 μm BiCMOS technology. Simulation results have shown that the new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications have better speed performance than that of CMOS and other BiCMOS dynamic logic circuits as the supply voltage is scaled down to 2 V. The operating frequency and power dissipation/MHz of the pipelined system, which is constructed by the new clock-high-evaluate-BiCMOS dynamic latch logic circuit and clock-low-evaluate-BiCMOS (BiNMOS) dynamic latch logic circuit, and the logic units with two stacked MOS transistors, are about 2.36 (2.2) times and 1.15 (1.1) times those of the CMOS TSPC dynamic logic under 1.5-pF output loading at 2 V, respectively. Moreover, the chip area of these two BiCMOS pipelined systems is about 1.9 times and 1.7 times as compared with that of the CMOS TSPC pipelined system. A two-input dynamic AND gate fabricated with 1 μm BiCMOS technology verifies the speed advantage of the new BiNMOS dynamic logic circuit. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed new dynamic logic circuits and dynamic latch logic circuits are feasible for high-speed, low-voltage dynamic pipelined system applications     

用于通信ASIC的高速BiCMOS逻辑电路

提出了几种通信用BiCMOS逻辑门电路的实现方案。这些逻辑门均可在低电源电压(2.0~3.0 V)下,采用BiCMOS工艺和深亚微米技术精心设计及制作,并经过比较对其作出评价。分析和实验结果表明,所设计的电路不但具有确定的逻辑功能,而且具备高速、低耗、低电源电压和全摆幅的特性,因而完全适用于高速数字通信系统中。     

一种高速低耗全摆幅BiCMOS集成施密特触发器

通过分析国外流行的一种 Bi CMOS集成施密特触发门 ,提出了一种高速、低功耗、全摆幅输出的Bi CMOS施密特触发器。该器件中单、双极型电路优势互补 ,电源电压为 1 .5 V,实现了优于同类产品的全摆幅输出 ,且其开关速度高于同类 CMOS产品的 1 3倍以上 ,因此特别适用于高速数字通信系统中     

A bootstrapped bipolar CMOS (B2CMOS) Gate forlow-voltage applications

This paper reports on a BiCMOS logic gate which combines bootstrapping and transient saturation techniques to achieve full swing operation down to 1.1 V supply voltage. The proposed B²CMOS uses a conventional (noncomplementary) BiCMOS process. HSPICE simulations have been used to compare the B²CMOS to CMOS, BiNMOS, and BS-BiCMOS for sub-0.5 μm BiCiMOS technologies. Simulation results have shown that the B²CMOS gate outperforms CMOS, BiNMOS, and BS-BiCMOS gates at 3 V and below. The crossover capacitance/fanout of the B²CMOS gate is 100 fF (i.e., fanout of 4) at 1.5 V. The delay-to-load sensitivity of the B²CMOS is 220 ps/pF (8 ps/fanout) which is one order of magnitude smaller than that of CMOS at 1.5 V     

An analytical transient model for a 1.5 V BiCMOS dynamic logiccircuit for low-voltage deep submicrometer BiCMOS VLSI

This paper presents an analytical transient model for the 1.5 V BiCMOS dynamic logic circuit using Gummel-Poon charge control model for deep submicrometer BiCMOS VLSI. Based on the analysis, the switching time of the 1.5 V BiCMOS dynamic circuit is sensitive to the forward transit time with a large load capacitance. With a small load capacitance, its switching time is related to the threshold voltage     

Novel low-voltage low-power full-swing BiCMOS circuits

A novel BiCMOS full-swing circuit technique with superior performance over CMOS down to 1.5 V is proposed. A conventional noncomplementary BiCMOS process is used. The proposed pull-up configuration is based on a capacitively coupled feedback circuit. Several pull-down options were examined and compared, and the results are reported. Several cells were implemented using the novel circuit technique; simple buffers, logic gates, and master-slave latches. Their performance, regarding speed, area, and power, was compared to that of CMOS for different technologies and supply voltages. Both device and circuit simulations were used. A design procedure for the feedback circuit and the effects of scaling on that procedure were studied and reported     

高速低压低功耗BiCMOS逻辑电路及工艺技术

介绍了几种高开关速度、低电源电压等级，低功耗的BiCMOS逻辑门电路，并分析了它们的工作原理及其工艺技术情况。结果表明，这些电路的电源电压可达到2．0V以下，而且信号传输延迟较小，有的还实现了全摆幅输出，因而它们可用于便携式电子设备和其它VLSI和ULSI新品等场合。     

Supply voltage design tradeoffs between speed and NMOSFETreliability of half-micrometer BiCMOS gates

Voltage supply scaling for a BiCMOS gate was investigated experimentally and analytically. For half-micrometer technology, the supply voltage design tradeoffs between propagation delay and NMOSFET reliability were studied. It was found that the minimum BiCMOS operating voltage ranges from 2.5 to 3.0 V. This minimum can be explained by the sum of twice the base-emitter potential and the NMOSFET threshold voltage, due to the emitter grounded Bi-MOS structure of the BiCMOS gate. As a result, 3.3-V operation is inherently marginal for BiCMOS gates. On the other hand, NMOS reliability in the BiCMOS gate is drastically improved because effective drain voltage is reduced by the base-emitter potential. Thus, NMOSFETs with a channel length shorter by more than 0.2 μm can be used, and this ensures reliable operation of BiCMOS gates at 5 V. In terms of the tradeoffs between gate speed and NMOS reliability, it is verified that BiCMOS gates offer the highest speed in half-micrometer design     

New full-voltage-swing BiCMOS buffers

Circuit techniques are presented for increasing the voltage swing of BiCMOS buffers through active charging and discharging using complementary bipolar drivers. These BiCMOS circuits offer near rail-to-rail output voltage swing, higher noise margins, and higher speed of operation at scaled-down power supply voltages. The circuits are simulated and compared to BiCMOS and CMOS buffers. The comparison shows that the conventional BiCMOS and the complementary BiCMOS buffers are efficient for power supply voltages greater than 3V and that if the power supply voltage is scaled down (<3 V) and the load capacitance is large (>1 pF), the complementary BiCMOS buffers would be the most suitable choice. They provide high speed and low delay to load sensitivity and high noise margins. The first implementation is favorable near a 2.5-V power supply for its smaller area     

Optimisation of BiCMOS buffers for low voltage applications

The numerical optimisation of existing low voltage BiCMOS buffer designs allows a valid comparison of performance. A new bootstrap BiCMOS buffer design, which combines temporary saturation and a bootstrap capacitor, is shown to be the fastest under all conditions. The new design operates down to a supply voltage of 1.1 V     

一种高精度BiCMOS电流模带隙基准源

采用Xfab0.35μmBiCMOS工艺设计了一种高电源抑制比（PSRR）、低温漂、输出0.5V的带隙基准源电路。该设计中,电路采用新型电流模带隙基准,解决了传统电流模带隙基准的第三简并态的问题,且实现了较低的基准电压;增加了修调电路,实现了基准电压的微调。利用Cadence软件对其进行仿真验证,其结果显示,当温度在-40～＋120℃范围内变化时,输出基准电压的温度系数为15ppm/℃;电源电压在2～4V范围内变化时,基准电压摆动小于0.06mV;低频下具有-102.6dB的PSRR,40kHz前电源抑制比仍小于-100dB。