A 1.5-V full-swing BiCMOS logic circuit

A BiCMOS logic circuit applicable to sub-2-V digital circuits has been developed. A transiently saturated full-swing BiCMOS (TS-FS-BiCMOS) logic circuit operates twice as fast as CMOS at 1.5-V supply. A newly developed transient-saturation technique, with which bipolar transistors saturate only during switching periods, is the key to sub-2-V operation because a high-speed full-swing operation is achieved to remove the voltage loss due to the base-emitter turn-on voltage. Both small load dependence and small fan-in dependence of gate delay time are attained with this technique. A two-input gate fabricated with 0.3-μm BiCMOS technology verifies the performance advantage of TS-FS-BiCMOS over other BiCMOS circuits and CMOS at sub 2-V supply     

A 1.5 V full-swing BiCMOS dynamic logic gate circuit suitable forVLSI using low-voltage BiCMOS technology

This paper presents a 1.5 V full-swing BiCMOS dynamic logic gate circuit, based on a dynamic pull-down BiPMOS configuration, suitable for VLSI using low-voltage BiCMOS technology. With an output load of 0.2 pf, the 1.5 V full-swing BiCMOS dynamic logic gate circuit shows a more than 1.8 times improvement in speed as compared to the CMOS static one     

A BiCMOS dynamic multiplier using Wallace tree reductionarchitecture and 1.5-V full-swing BiCMOS dynamic logic circuit

The authors present a BiCMOS dynamic multiplier, which is free from race and charge-sharing problems, using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit. Based on a 1-μm BiCMOS technology, a 1.5-V 8×8 multiplier designed, shows a 2.3× improvement in speed as compared to the CMOS static one     

A 1.5-V differential cross-coupled bootstrapped BiCMOS logic forlow-voltage applications

Two new bipolar complementary metal-oxide-semiconductor (BiCMOS) differential logic circuits called differential cross-coupled bootstrapped BiCMOS (DC²B-BiCMOS) and differential cross-coupled BiCMOS (DC²-BiCMOS) logic are proposed and analyzed. In the proposed two new logic circuits, the novel cross-coupled BiCMOS buffer circuit structure is used to achieve high-speed operation under low supply voltage. Moreover, a new bootstrapping technique that uses only one bootstrapping capacitor is adopted in the proposed DC²B-BiCMOS logic to achieve fast near-full-swing operation at 1.5 V supply voltage for two differential outputs. HSPICE simulation results have shown that the new DC²B-BiCMOS at 1.5 V and the new DC²-BiCMOS logic at 2 V have better speed performance than that of CMOS and other BiCMOS differential logic gates. It has been verified by the measurement results on an experimental chip of three-input DC²B-BiCMOS XOR/XNOR gate chain fabricated by 0.8 μm BiCMOS technology that the speed of DC²-BiCMOS at 1.5 V is about 1.8 times of that of the CMOS logic at 1.5 V. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed DC²B-BiCMOS and DC²-BiCMOS logic circuits are feasible for low-voltage, high-speed applications     

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump

A BiCMOS logic circuit with very small input capacitance has been developed, which operates at low supply voltages. A High-beta BiCMOS (Hβ-BiCMOS) gate circuit which fully utilizes the bipolar transistor features achieves 10 times the speed of a CMOS gate circuit with the same input capacitance and operating at 3.3 V supply voltage. In order to lower the minimum supply voltage of Hβ-BiCMOS, a BiCMOS circuit configuration using a charge pump to pull up the output high level of the BiCMOS gate circuit is proposed. By introducing a BiCMOS charge pump, Hβ-BiCMOS achieves very high speed operation at sub-2.0 V supply voltage. It has also been demonstrated that only a very small number of charge pump circuits are required to drive a large number of Hβ-BiCMOS gate circuits     

1.5 V CMOS full-swing energy efficient logic (EEL) circuit suitablefor low-voltage and low-power VLSI applications

A 1.5 V full-swing energy efficient logic circuit is reported that is suitable for next-generation low-power VLSI applications using a low supply voltage. At 25 MHz and at 1.5 V, the power consumption of the EEL circuit is 70% of that for an ECRL circuit and 47% of that for the static circuit     

BiCMOS logic circuit for single-battery operation

A novel BiCMOS logic circuit is described that provides highspeed rail-to-rail operation with only one battery cell (1-1.5 V). The proposed circuit utilises a novel pull-down scheme that involves bootstrapping the base of the pull-down p-n-p bipolar junction transistor to a negative potential during the pull-down transient period. Circuit simulations have shown that the proposed circuit outperforms the transient-saturation full-swing BiCMOS and the bootstrapped bipolar circuits in terms of delay, power and cross-over capacitance for all simulated supply voltages     

A 1.5-V full-swing bootstrapped CMOS large capacitive-load drivercircuit suitable for low-voltage CMOS VLSI

This paper reports a 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit using two bootstrap capacitors to enhance the switching speed for low-voltage CMOS VLSI. For a supply voltage of 1.5 V, the full-swing bootstrapped CMOS driver circuit shows a 2.2 times improvement in switching speed in driving a capacitive load of 10 pF as compared to the conventional CMOS driver circuit. Even for a supply voltage of 1 V, this full-swing bootstrapped CMOS large capacitive-load driver circuit is still advantageous     

Bootstrapped full-swing BiCMOS/BiNMOS logic circuits for 1.2-3.3 Vsupply voltage regime

Novel full-swing BiCMOS/BiNMOS logic circuits using bootstrapping in the pull-up section for low supply voltage down to 1 V are reported. These circuit configurations use noncomplementary BiCMOS technology. Simulations have shown that they outperform other BiCMOS circuits at low supply voltage using 0.35 μm BiCMOS process. The delay and power dissipation of several NAND configurations have been compared. The new circuits offer delay reduction between 40 and 66% over CMOS in the range 1.2-3.3 V supply voltage. The minimum fanout at which the new circuits outperform CMOS gate is 5, which is lower than that of other gates particularly for sub-2.5 V operation     

1.5 V high-speed electrostatic discharge free BiCMOS digitalcircuit

A novel circuit design that effectively eliminates the need for input protection circuits is described. Besides having an excellent electrostatic discharge (ESD) robustness, the simulation results have shown that this design outperforms current BiCMOS circuits in terms of speed, power, crossover capacitance, and chip area for a wide range of load capacitances, power supply voltages and technologies. The proposed circuit remains functional after an ESD test     

1.5V高速全摆幅BiCMOS逻辑电路的研究

分析了影响ＢｉＣＭＯＳ全摆幅输出和高速度的因素,探索了一种新的抑制ＢＪＴ过饱和和反馈网络,提出了具有高速全摆幅输出的ＢｉＣＭＯＳ逻辑单元。该单元可以工作于１．５Ｖ,并且易于多输入扩展,它特别适于ＶＬＳＩ设计。模拟结果表明,该单元实现了优于ＣＭＯＳ的全摆幅输出,且其速度高于同类ＣＭＯＳ电路１０倍以上。     

An analytical transient model for a 1.5 V BiCMOS dynamic logiccircuit for low-voltage deep submicrometer BiCMOS VLSI

This paper presents an analytical transient model for the 1.5 V BiCMOS dynamic logic circuit using Gummel-Poon charge control model for deep submicrometer BiCMOS VLSI. Based on the analysis, the switching time of the 1.5 V BiCMOS dynamic circuit is sensitive to the forward transit time with a large load capacitance. With a small load capacitance, its switching time is related to the threshold voltage     

1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture

A 1.5V BiCMOS dynamic multiplier is presented which is free from race and charge sharing problems, using Wallace tree reduction architecture and a 1.5V full-swing BiCMOS dynamic logic circuit. Based on a 1 mu m BiCMOS technology, a designed 1.5V 8*8 multiplier shows a *2.3 improvement in speed as compared to the CMOS static multiplier.<>     

Low-voltage dynamic BiCMOS CLA circuit with carry skip using novelfull-swing logic

This paper presents novel low-voltage dynamic BiCMOS logic gates and an improved carry look-ahead (CLA) circuit with carry skip using these new dynamic BiCMOS topologies. The well-known “MOS clock feedthrough effect” is used to achieve full swing with substantially reduced low-to-high evaluation delay in the logic gates, thus, resulting in reduced carry propagation/bypass delay in the cascaded CLA array. Simulations at clocking frequency of 100 MHz, using 2-μm BiCMOS process parameters and supply voltage in the range of 2-4 V displays lower gate delay and lower power dissipation compared to other recent dynamic BiCMOS logic topologies. The circuit has no dc power dissipation, race, or charge redistribution problems. An 8-b CLA with 5-b carry skip was achieved in 2.917 ns. This speed is significantly higher than other recent dynamic BiCMOS CLA designs. In addition, the new CLA circuit is more compact compared to previous dynamic BiCMOS CLA designs. A tiny chip was fabricated using the MOSIS Orbit Analog 2-μm V-well CMOS process for the experimental verification of the new low-voltage dynamic BiCMOS topologies     

A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates

A 1.5-ns address access time, 256-kb BiCMOS SRAM has been developed. To attain this ultra-high-speed access time, an emitter-coupled logic (ECL) word driver is used to access 6-T CMOS memory cells, eliminating the ECL-MOS level-shifter time delay. The RAM uses a low-power active pull down ECL decoder. The chip contains 11-K, 60-ps ECL circuit gates. It provides variable RAM configurations and general logic functions. RAM power consumption is 18 W; chip power consumption is 35 W. The chip is fabricated by using a 0.5-μm BiCMOS process. The memory cell size is 58 μm² and the chip size is 11×11 mm     

7.5V高精度BiCMOS电压调整器的设计

提出一种应用于有源功率因数校正控制芯片的7.5 V高精度线性电压调整器的设计.由于采用了多种改进措施,包括片上微调电阻网络的应用,该调整器具有良好的电压调整特性和很高的温度稳定性.此外,调整器还集成了过流保护功能.该电路采用1.5μm BiCMOS工艺设计实现,面积为0.42 mm×0.63 mm.测试结果表明,在12 V供电电压下,当负载电流在0～20 mA范围内变化时,其负载调整率达23%/A.片上微调电阻的应用使其可获得很低的温度系数.     

A 2.5-V 45-Gb/s decision circuit using SiGe BiCMOS logic

A 45-Gb/s BiCMOS decision circuit operating from a 2.5-V supply is reported. The full-rate retiming flip-flop operates from the lowest supply voltage of any silicon-based flip-flop demonstrated to date at this speed. MOS and SiGe heterojunction-bipolar-transistor (HBT) current-mode logic families are compared. Capitalizing on the best features of both families, a true BiCMOS logic topology is presented that allows for operation from lower supply voltages than pure HBT implementations without compromising speed. The topology, based on a BiCMOS cascode, can also be applied to a number of millimeter-wave (mm-wave) circuits. In addition to the retiming flip-flop, the decision circuit includes a broadband transimpedance preamplifier to improve sensitivity, a tuned 45-GHz clock buffer, and a 50-/spl Omega/ output driver. The first mm-wave transformer is employed along the clock path to perform single-ended-to-differential conversion. The entire circuit, which is implemented in a production 130-nm BiCMOS process with 150-GHz f/sub T/ SiGe HBT, consumes 288 mW from a 2.5-V supply, including only 58 mW from the flip-flop.     

Logic circuit design using monostable-bistable transition logic element based on standard BiCMOS process

We present a monostable-bistable transition logic element (MOBILE) based on the negative-differential-resistance (NDR) circuit. In particular, this circuit can be completely implemented using the standard BiCMOS process. A traditional MOBILE using two resonant tunneling diodes (RTD) connected in series is a functional logic circuit. The fabrication of RTD is utilized in the complicated molecular-beam-epitaxy (MBE) system. However, we present a MOBILE circuit that is completely made of standard Si-based metal-oxide-semiconductor field effect transistors and SiGe-based heterojunction bipolar transistors. By suitably determining the control voltages and input conditions, we can obtain the operation of the inverter, AND and OR logic gates. We also demonstrate the latch characteristic of this MOBILE circuit. This logic circuit is fabricated using the standard 0.35 μm BiCMOS process without the need for the MBE system.     

BiCMOS三态输出门电路的设计、制备及应用

设计了几种BiCMOS三态输出门电路,提出了采用先进的0.5μm BiCMOS工艺,制备所设计的三态输出门的技术要点和器件参数,并分析了它们既具有双极型(Bipolar)门电路快速、大电流驱动能力,又具备CMOS逻辑门低压、低功耗和高集成度的特性,因而它们特别适用于高速缓冲数字信息系统和其它便携式数字设备中.     

BiCMOS circuit technology for a high-speed SRAM

BiCMOS circuit technology for a high-speed and large-capacity ECL-compatible static RAM (SRAM) is described. To obtain high-speed and low-power operation, a decoder with a pre-main decode configuration having an ECL-interface circuit and a word driver with BiCMOS inverter are proposed. A BiCMOS multiplexer with a single emitter-follower driver is also proposed. An optimization method for memory cell array configuration is presented that minimizes the total delay time and the total power dissipation of SRAMs. Circuit simulation results show that a 64-kbit ECL-compatible SRAM with an access time of less than 7 ns and a power dissipation of less than 1 W is obtainable