Σ-Δ模拟/数字转换器综述

Σ-ΔA/D转换器是利用速度换取精度的高精度模拟/数字转换器。文章分析了Σ-ΔA/D转换器的产生、组成和优势,重点介绍了Σ-Δ调制器结构及其性能指标,简要介绍了数字抽取滤波器。对Σ-ΔA/D转换器国内外发展状况进行了全面的分析。在此基础上,论述了Σ-ΔA/D转换器未来的发展趋势。     

一种利用流水并行比较法的A／D转换器

提出和验证了一种利用新型流水并行式模数转换法的A／D转换器（ADC）。在达到并行比较式ADC相同转换时间tc的前提下，流水并行式ADC的tc和n函数关系等同于并行比较式ADC，而其m和n函数关系优于并行比较式ADC，并且比流水式ADC易于实现。介绍了流水并行式ADC的电路设计和具体实现的要点，给出了相应的ADC易于实现。介绍了流水并行式ADC的电路设计和具体实现的要点，给出了相应的ADC实验结果和时序。     

一种应用于脉冲式激光雷达的模拟存储ADC芯片

设计了一种应用于脉冲式激光雷达系统中基于模拟存储原理的模数转换器(ADC)芯片。介绍了ADC在激光雷达中的功能原理,设计搭建了高速时序控制电路和模拟存储阵列,并配合设计了低速流水线ADC内核电路和附属的PLL模块。仿真结果表明,该模拟存储ADC电路在激光雷达的具体应用中,可用25 MHz的低速ADC达到1.6 GHz ADC的等效功能。     

用FIFO实现高速模数转换器与TMS320C6000系列DSP的接口

说明了如何使用CY7C4265-10AC FIFO来实现TMS320C6205与AD9042AST模数转换器的接口。详细介绍了TMS320C6205读取FIFO中数据的速度以及如何设置EMIF的CExCTL寄存器的接口时序。     

8通道12位串行A/D转换器MAX1202及其应用

介绍了８通道１２位串行Ａ／Ｄ转换器ＭＡＸ１２０２的功能特点和工作过程,并以材料表面喷涂金属薄膜自动控制系统为例,给出了ＭＡＸ１２０２与ＡＴ８９Ｃ２０５１的接口电路及软件设计。     

应用于ΣΔADC的多级抽取滤波器面积有效实现方法

本文介绍了一种用于音频过采样模数转换器的多级抽取滤波器的面积有效实现方法。抽取滤波器的抽取倍数为256,通带波纹小于0.005dB,阻带抑制达到100dB。通带范围为0-20kHz,输出为48kHz的16比特信号。通过采用含RAM和ROM的面积有效架构,以及对一个运算周期中有效的指令调度,该抽取滤波器在XilinxFPGA上综合后仅使用了不到300个LUT和不到160个Slice。不同于串行或部分串行架构中运算速率通常大于输入采样速率的情况,该实现方法可使得运算速率和采样速率一致,从而简化整体ΣΔADC设计并降低功耗。架构中RAM和ROM的采用使得该抽取滤波器可编程,进一步可改进用于自适应滤波应用。最后,在Modelsim中的RTL仿真结果通过Matlab\Simulink程序进行了验证。     

单片机与串口D/A转换器MAX525的接口设计

简要介绍了MAXIM公司生产的串口4通道D／A转换器MAX525的基本原理及功能特点，给出了MAX525与单片机AT89C52接口的硬件电路及软件编程实例。     

基于单片机的接口转换设计及应用

论述了用AT89C51单片机控制Intel8251A和MC68488接口芯片来实现RS232C与通用接口总线GPIB（general-purpose interface bus）接口之间的转换设计，并将其应用到印制电路板程控探针定位设备中。     

一种8位1 GS/s折叠内插A/D转换器

基于TSMC 0.18 μm CMOS工艺,采用两级级联的折叠内插结构,设计了一种8位1 GS/s折叠内插A/D转换器。在预放大器阵列输出端引入失调平均网络,优化了预放大器阵列的输入对管尺寸,以补偿边界预放大器的增益衰减。在折叠电路中引入幅度补偿电路,以增加较小的电路功耗为代价改善了电路的带宽限制,提高了增益及输出线性范围。分析了内插平均电阻网路中的高倍内插误差,通过优化内插电阻值,实现了内插输出失调的减小,保证了系统良好的精度特性。仿真结果表明,在采样率为1 GS/s、输入正弦波频率为465.82 MHz的条件下,该8位折叠内插A/D转换器的有效位数能够达到7.31位,功耗为290 mW。     

An 8-bit 20-MS/s ZCBC Time-Domain Analog-to-Digital Data Converter

An 8-bit 20-MS/s time-domain analog-to-digital data converter (ADC) using the zero-crossing-based circuit technique is presented. Compared with the conventional ADCs, signal processing is executed in both the voltage and time domains. Since no high-gain operational amplifier is needed, this time-domain ADC works well in a low supply voltage. The proposed ADC has been fabricated in a 0.18-mum CMOS process. Its power dissipation is 4.64 mW from a supply voltage of 1.8 V. This active area occupies 1.2 times 0.7 mm². The measured signal-to-noise-distortion ratio achieves 44.2 dB at an input frequency of 10 MHz. The integral nonlinearity is less than plusmn1.07 LSB, and the differential nonlinearity is less than plusmn0.72 LSB. This time-domain ADC achieves the effective bits of 7.1 for a Nyquist input frequency at 20 MS/s.     

一种改进的高速高精度ADC数字校准算法

提出一种能快速收敛并具有鲁棒性的流水线模数转换器(ADC)数字校准方法。设计的ADC采用12级1.5位/级MDAC和一个6位高精度SAR ADC的结构。采用Altera FPGA,对该算法进行了验证。结果表明,用该方法校准的A/D转换器,在90.55 MHz输入频率下,SNDR可达到84 dB,DNL为-0.59/0.28 LSB,INL为-0.59/0.34 LSB。     

用于CMOS低中频GPS接收机的模数转换器的设计考虑与实现

首先对用于CMOS低中频GPS接收机的模数转换器(ADC)进行了设计考虑.由ADC引入的信噪比降低与四个因素有关:中频带宽,采样率,ADC的比特数及ADC的最大阈值与噪声均方根比值.在设计考虑的基础上,采用TSMC 0.25tan CMOS单层多晶硅五层金属工艺实现了一个4 bit 16.368 MHz闪烁型模数转换器,并将重点放在了前置放大器和提出的新的比较器的设计和优化上.在时钟采样率16.368 MHz和输入信号频率4.092 MHz的条件下,转换器测试得到的信噪失真比为24.7 dB,无杂散动态范围为32.1 dB,积分非线性为 0.31/-0.46LSB,差分非线性为 0.66/-0.46LSB,功耗为3.5mW.ADC占用芯片面积0.07 mm2.     

Correction of Mismatches in a Time-Interleaved Analog-to-Digital Converter in an Adaptively Equalized Digital Communication Receiver

In this paper, techniques to overcome the errors caused by the offset, gain, sample-time, and bandwidth mismatches among time-interleaved analog-to-digital converters in a high-speed baseband digital communication receiver are presented. The errors introduced by these mismatches are corrected using least-mean-square adaptation implemented in digital-signal-processing blocks. Gain, sample-time, and bandwidth mismatches are corrected by modifying the operation of the adaptive receive equalizer itself to minimize the hardware overhead. Simulation results show that the gain, offset, sample-time, and bandwidth mismatches are sufficiently corrected for practical digital communication receivers.      

An 8-Bit Flash Analog-to-Digital Converter in Standard CMOS Technology Functional From 4.2 K to 300 K

This paper presents the first Flash analog-to-digital converter (ADC) in standard CMOS technology that functions from 300 $~$K (room temperature) down to 4.2$~$K. It has been designed to operate in cryogenic sensor systems as they are cooled from room temperature to their final cryogenic operating temperature. In order to preserve the circuit's performance over this wide temperature range, even in the presence of temperature-induced transistor anomalies, dedicated architecture and switching schemes are employed. SPICE models for adequate circuit simulation at 4.2 K have been extracted. A first prototype of the chosen architecture, an 8-bit ADC in a standard 0.7$ muhbox{m}$ CMOS technology, achieves a differential nonlinearity (DNL) of 0.5 LSB at room temperature and 1 LSB at 4.2 K at a sampling frequency of 12.5 kHz.      

带串行控制的四路8位数/模转换器 TLC5620C 及其与单片机的接口

TLC5620C是美国德州仪器（TI）公司推出的带串行控制的四路8位数/模转换器。该转换器中的每一路均有输入锁存器和DAC锁存器等两级缓冲器，同时具有一个输出量程开关，一个8位DAC电路以及一个电压输出电路，文中分析了TLC5620C的组成与工作原理，介绍了该器件与TAT89C52单片机的硬件接口电路和软件编程，同时给出了一个应用实例。     

数据通信接口转换器能效参数和测试方法标准简介

首先讨论了数据通信接口转换器在通信网的位置以及通信设备节能的重要性,然后针对数据通信接口转换器的节能特性做了较深的研究,最后对即将发布的数据通信接口转换器能效参数标准做了全面介绍。     

Master–Slave Current-Sharing Control of a Parallel DC–DC Converter System Over an RF Communication Interface

Using analog wireless communication, we demonstrate a master-slave load-sharing control of a parallel dc-dc buck converter system, thereby eliminating the need for physical connection to distribute the control signal among the converter modules. The current reference for the slave modules is provided by the master module using radio-frequency (RF) transmission, thereby ensuring even sharing of the load current. The effect of delay due to RF transmission on system stability and performance is analyzed, and regions of operation for a stable as well as satisfactory performance are determined. We experimentally demonstrate a satisfactory performance of the master-slave converter at 20-kHz switching frequency under steady state as well as transient conditions in the presence of a transmission delay. The proposed control concept, which can potentially attain redundancy that is achievable using a droop method, may lead to more robust and reconfigurable control implementation of distributed converters and power systems. It may also be used as a (fault-tolerant) backup for wire-based control of parallel/distributed converters.     

An Extended Service Filtering Technique for Mass Calling-Type Services Using Intelligent Peripheral in an SCP-Bound Network

This paper proposes an extended service filtering technique to prevent overload in service control point (SCP) due to televoting (VOT) or mass calling (MAS) services with the heavy traffic characteristics. Also, this paper compares this extended technique with the existing overload control techniques, and calculates steady state call blocking probabilities in intelligent network (IN) under overload conditions. The proposed technique considers SCP overload and IN Capability Set (CS)-1 services (such as VOT or MAS service) that have to use the specialized resources of intelligent peripheral (IP). This technique uses first an activating step in which SCP requests service filtering to service switching point (SSP). Then, in the filtering step, SSP sends filtering results to SCP periodically or each Ncalls. Also, when filtering time-out expires, SSP stops service filtering, and sends service filtering response to SCP in the deactivating step. This paper applies this technique to VOT/MAS service, and calculates SCP and SSP-IP (circuit) call blocking probabilities by using an analytical VOT/MAS service model. With the modeling and analyzing of this new technique, it shows that this technique reduces the traffic flow into SCP from SSP and IP prominently.