Thermal placement algorithm based on heat conduction analogy

A thermal force-directed placement algorithm, called TFPA, based on heat conduction analogy, is proposed for MCM design. TFPA begins with the transformation of the real substrate with chips into an unbounded substrate with an infinite number of chips. Then, each chip pushes every other chip with a force based on the heat conduction analogy. Thus, each chip will move in the direction of the force until the system achieves equilibrium. TFPA generates high quality placement results and maintains a cooler and uniform thermal profile, by distributing chip powers as evenly as possible. Unlike conventional force-directed algorithms, which might have serious component overlapping problems, TFPA places chips apart and only little or even no overlap occurs. In practice, the initial placements obtained by TFPA are very close to final placements.     

A reliability-driven placement procedure based on thermal-force model

This paper deals with placing chips on an MCM substrate in chip array style for minimizing the system failure rate. The placement procedure begins with constructing an initial placement based on cooling considerations. Then, a thermal-force model is presented to transform the reliability-driven placement problem to solve a set of simultaneous nonlinear equations to determine thermal-force-equilibrium locations of the chips. A modified Newton–Raphson method is used to solve this system of equations. Finally, a chip assignment procedure transforms the thermal-force-equilibrium placement into an array style placement for minimum thermal distortion. Two assignment methods are developed and compared each other. Experiments on three industrial MCMs designed by IBM show that the obtained placements have significant improvements to their original designs in system reliability. Additionally, a simulated annealing approach is presented for justifying the performance of the proposed method.     

Response Surface Based Optimization Approach for Thermal Placement Design of Chips in Multiple-Chip Modules

This paper attempts to perform thermal enhancement of planar multiple-chip modules (MCMs) containing a number of chips of equal and/or unequal power through optimal chip placement design. To achieve the goal, an effective design approach is presented for the thermal design optimization problems in the context of models of placement of chips in MCMs. The approach combines the use of the currently proposed response surface (RS) based methodology, which is an optimization algorithm and a finite element modeling technique. The proposed RS-based methodology is used for creating a macro mathematical expression of the design objective of the thermal optimization problem, i.e., the total chip junction temperature of the system, associated with the design parameters, including the chip location and power. The validity of the mathematical expressions constructed is verified through two approaches. Furthermore, to make the constructed mathematical expression more compact while maintaining the associated solution accuracy, the backward variable elimination technique is employed. The effectiveness of the proposed design optimization methodology is demonstrated through several design case studies involving planar plastic ball grid array type MCMs. It is found that the proposed RS-based methodology could accurately define the macro mathematical model of the total system chip junction temperature in terms of the chip location and power. In addition, results show that the current optimal chip placement design can provide a minimal system temperature.     

SPLASH: A framework for chip design and layout

SPLASH is a library-based environment for the design and layout of VLSI chips. The program for placement and routing embedded in SPLASH belongs to the class of standard-cell based systems; however, many improvements over the conventional standard-cell approach have been introduced, such as hierarchy, lack of restrictions on the location of the terminals in the cells (provided that they are on the cell boundaries) and automatic power and ground routing. The most significant feature of this system is its speed, because layouts of very complex chips can be generated in a few minutes. A chip with more than 3000 interconnections can be laid out in less than 8 minutes. SPLASH consists of three programs: SLIB, a library assembler, SNET, the net-list parser/builder and BRUTUS, a program for both interactive and fully automatic placement and routing, BRUTUS is Manhattan-rule based. Presently, SPLASH supports both nMOS and CMOS technologies.     

Multidisciplinary heat generating logic block placement optimization using genetic algorithm

A multidisciplinary optimization methodology for placement of heat generating semiconductor logic blocks on integrated circuit chips is presented. The methodology includes thermal and wiring length criteria, which are optimized simultaneously using a genetic algorithm. An effective thermal performance prediction methodology based on a superposition method is used to determine the temperature distribution on a silicon chip due to multiple heat generating logic blocks. Using the superposition method, the predicted temperature distribution in the silicon chip is obtained in much shorter time than with a detailed finite element model and with comparable accuracy. The main advantage of the present multidisciplinary design and optimization methodology is its ability to handle multiple design objectives simultaneously for optimized placement of heat generating logic blocks. Capabilities of the present methodology are demonstrated by applying it to several standard benchmarks. The multidisciplinary logic block placement optimization results indicate that the maximum temperature on a silicon chip can be reduced by up to 7.5 °C, compared to the case in which only the wiring length is minimized.     

Reliability and routability consideration for MCM placement

This paper presents a methodology based on the fuzzy logic approach for the placement of the power dissipating chips on the multichip module substrate. Our methodology considers both thermal distribution and routing length constraints during multichip module placement. In this paper, the main design issue is the coupled placement for reliability and routability. The objective of the coupled placement is to enhance the system performance and reliability by obtaining an optimal cost during multichip module placement. For reliability considerations, the design methodology is addressed on the placement of the power dissipating chips to achieve uniform thermal distribution. The thermal placement analysis is based on the modified fuzzy force-directed placement method. Placement for routability is based on minimizing the total wire length estimated by semi-perimeter method. The placement trade-off between routability and reliability is illustrated by varying a weighting factor. Case studies of the coupled placement are presented. In addition, the thermal distribution of the coupled placement results is simulated with the finite element method.     

A Force-Directed-Based Optimization Scheme for Thermal Placement Design of MCMs

Thermal management becomes exceptionally critical to both the reliability and operation performance of electronic packages, particularly for multichip modules (MCMs), as packaging and power densities continue increase while packaging dimension continues decrease. The underlying goal of the study is to pursue the minimum system temperature design of MCMs containing a number of chips of equal and/or unequal power through the optimal chip placement design. To deal with the thermal design problems, an effective indirect optimization approach that integrates a modified force-directed (FD) thermal model, a finite-element (FE) technique and an exterior penalty method (EPM) is proposed. In the modified FD thermal model, a novel representation of the repulsive and attractive forces is proposed, and the sum of these forces in the design system, representing the total system chip junction temperature, constructs the objective of the optimization problems. Together with some geometry constraints, the constrained optimization problems are formed, and furthermore, transformed into unconstrained optimization problems using an EPM. The solution of the optimization problems is sought through a direct, iterative search scheme with two proposed placement strategies. The alternative goal of the study is to address the feature and feasibility of these two proposed placement strategies for the current problems. The applicability of the proposed optimization approach is demonstrated through several design applications, and their results are extensively compared against the published data. It turns out that the current optimization approach can be very effective and robust in providing thermal optimal design of MCMs with a minimal total chip junction temperature through optimal chip placement     

Design of multichip modules

The process and pitfalls of multichip module (MCM) design, including the constraints, tradeoffs, figures of merit, and considerations which make MCM design a unique interdisciplinary challenge are discussed. The MCM must provide the proper operating environment for the chips it contains. It must also fit the constraints of the system in which it is contained. It must be manufacturable, testable, and repairable. The many aspects of MCM design are described, starting with system benefits, then system and MCM partitioning, chip environment, system constraints, and infrastructure/manufacturing issues     

Z900MCM综述

介绍了Z900 MCM设计和布局,可控塌陷芯片连接(C4)工艺在Z900 MCM组装中的应用。从设计上通过加入垂直电感器及去耦电容器减小其噪声。通过基板测试和功能测试,剔除有缺陷的基板和芯片。Z900 MCM采用先进的MCM—D技术和MCM返工及冷却技术。Z900 MCM平均无故障时间高达40年。     

A novel switchable pin method for regulating power in chip-multiprocessor

Transistor scaling has allowed a large number of circuits to be integrated into integrated circuit (IC) chips implemented in nanometer CMOS technology nodes. However, dark silicon which signifies for under-utilized circuitry will become dominant in future chips due to limited thermal design power (TDP). Furthermore, large voltage loss due to complex routing and placement will also degrade the performance of ICs. In addition, effectively managing power dissipation in a packaged chip is one of the major issues of IC design. Previous work done by our group mainly focused on RCL simulation and elementary IC simulation, this work not only builds on power delivery network (PDN), but also designs switchable pin working for two cores at the layout level. The essence of our idea is to supply power to the chip using traditional I/O pads. In order to balance power supply and I/O bandwidth, we set several groups of parallel switchable pins between the core and memory such that I/O pads can dynamically switch between two modes which are data transmission and power supply. To remove the risk that large current going through I/O pad breaks down the pad frame, we redesigned traditional I/O pad to operate in bi-direction. Using TSMC CMOS 180 nm process for the design and simulation, our test results show that the proposed switchable pin can well compensate voltage loss in chip multiprocessor, and transfer time of two modes is very short. For data transmission, we perform a sensitivity study to explore the impact brought by switchable pins. Our simulation results demonstrate that performance degradation is in acceptable range when the switchable pins are added to the chip-multiprocessor.     

用模拟退火算法实现集成电路热布局优化

介绍了一种综合考虑集成电路电学性能指标以及热效应影响的布局优化方法 .在保证传统设计目标 (如芯片面积、连线长度、延迟等 )不被恶化的基础上 ,通过降低或消除芯片上的热点来优化集成电路芯片的温度分布情况 ,进而优化整个电路性能 .并将改进的模拟退火算法应用于集成电路的热布局优化 ,模拟结果表明该方法与传统布局方法相比在保持了较好的延迟与连线长度等设计目标的同时 ,很好地改善了芯片表面的热分配情况     

Fuzzy thermal modeling for MCM placement

This paper introduces a fuzzy analytical model for the optimal component placement of the power dissipating chips on a multichip module substrate. Our methodology considers multiobjective component placement based on thermal reliability as well as routing length criteria. The objective of the coupled placement methodology is to enhance the performance and reliability of the multichip module system by obtaining an optimal cost during multichip module placement. Case studies of the coupled placement are presented. In addition, the thermal distribution of the coupled placement results is simulated using the finite element method.     

Net Congestion Elimination for Datapaths by Placement Refinement

The layout of datapaths is much complexer than that of a normal IC chips, because more constraints must be considered. A novel method for eliminating the net congestion of datapath chips is presented. The main idea is to modify the placement locally according to the global routing result. The problem is abstracted to a nonlinear programming problem and could be transformed to a convex one. Experimental results demonstrate that the method can eliminate the net congestion of datapath chips effectively     

基于FPGA伪随机码发生器的实现

文章讨论了在FPGA上利用线性反馈移位寄存器实现伪随机码发生器的方法,运用VHDL语言描述各部分的设计,这样不但利于随时修改而且还节省了设计的周期和简化了整个设计。此设计以Altera公司的QuartusⅡ为开发平台,经逻辑综合、布局布线后,适配到FPGA芯片中,给出了仿真结果,最后还给出了在示波器上显示的波形及其相关的分析。     

Net Congestion Elimination for Datapaths by Placement Refinement

The datapath chip is a special species of IC chips.Datapath circuits are widely used incomputer systems and communication systems as a data processor.Because there existmore constraints,the layout of datapaths is much complexer than ...     

Present and future directions for multichip module technologies

Multichip modules (MCM's) have been actively developed in recent years. They are expected to provide high-performance systems by packing bare chips at a high density. In particular, a thin-film interconnect substrate that can accommodate higher wiring capacity in a few layers is a new option for coping with high pin count and fine pad pitch VLSI's. MCM's require various kinds of technologies including the fabrication processes of interconnect substrates, chip connection methods, electrical design, thermal management, known good die (KGD), and so on. The state of the art of MCM technologies is reviewed and future directions are discussed     

Test structures for MCM-D technology characterization

In this paper we present a set of classic and novel test structures addressed to fully characterize multichip module (MCM) technologies. The structures have been implemented and fabricated in our D-type, flip-chip, ball grid array, silicon substrate technology. In this technology, a silicon chip is used as a substrate on which other commercial chips are flipped and soldered by a screen-printing method. These complex technologies have specific test problems that are solved with this approach. We have specially focused on the measurement of the effects of wafer rerouting on CMOS parameters, the chip-to-chip ball contact resistance, thermal behavior, yield, and reliability of the technology. Experimental results are shown, proving that this methodology is suitable for our technology and can also be applied to other different MCM technologies     

基于埋置式基板的3D-MCM封装结构的研制

研制一种用于无线传感网的多芯片组件（3D-MCM) . 采用层压、开槽等工艺获得埋置式高密度多层有机（FR-4）基板,通过板上芯片（COB) 、板上倒装芯片（FCOB) 、球栅阵列（BGA）等技术,并通过引线键合、倒装焊等多种互连方式将不同类型的半导体芯片三维封装于一种由叠层模块所形成的立体封装结构中;通过封装表层的植球工艺形成与表面组装技术（SMT）兼容的BGA器件输出端子;利用不同熔点焊球实现了工艺兼容的封装体内各级BGA的垂直互连,形成了融合多种互连方式3D-MCM封装结构. 埋置式基板的应用解决了BGA与引线键合芯片同面组装情况下芯片封装面高出焊球高度的关键问题. 对封装结构的散热特性进行了数值模拟和测试,结果表明组件具有高的热机械可靠性. 电学测试结果表明组件实现了电功能,从而满足了无线传感网小型化、高可靠性和低成本的设计要求.     

MCM封装技术中的基板设计与分析

通过采用多芯片组件封装技术,将6种由不同集成电路工艺实现的不同类型的芯片集成在单个封装内,简化了系统设计,实现了产品小型化的目标。同时,还详细给出了Zeni EDA工具下的MCM基板设计流程以及MentorPCB环境下的多芯片组件热分析方法。     

表面响应法在埋置型大功率多芯片微波组件热布局中的应用研究

该文将有艰元模拟与基于统计试验的表面响应法(RSM)相结合,应用于特定需求的埋置型大功率多芯片微波组件热布局分析中,先通过ANSYS温度场分析,得出大功率芯片布局是影响整体温度和芯片结温的关键因素,再对一含有四个大功率芯片的微波组件模块进行了表面响应分析,得到了关于芯片坐标的线性回归方程,利用该方程可预测坐标组合下芯片...