An ATM routing and concentration chip for a scalable multicast ATMswitch

We have proposed a new architecture for building a scalable multicast ATM switch from a few tens to a few thousands of input/output ports. The switch, called the Abacus switch, employs input and output buffering schemes. Cell replication, cell routing, and output contention resolution are all performed in a distributed way so that the switch can be scaled up to a large size. The Abacus switch adopts a novel algorithm to resolve the contention of both multicast and unicast cells destined for the same output port (or output module). The switch can also handle multiple priority traffic by routing cells according to their priority levels. This paper describes a key ASIC chip for building the Abacus switch. The chip, called the ATM routing and concentration (ARC) chip, contains a two-dimensional array (3×32) of switch elements that are arranged in a cross-bar structure. It provides the flexibility of configuring the chip into different group sizes to accommodate different ATM switch sizes. The ARC chip has been designed and fabricated using 0.8-μm CMOS technology and tested to operate correctly at 240 MHz, Although the ARC chip was designed to handle the line rate at OC-3 (155 Mb/s), the Abacus switch can accommodate a much higher line rate at OC-12 (622 Mb/s) or OC-48 (2.5 Gb/s) by using a bit-sliced technique or distributing cells in a cyclic order to different inputs of the ARC chip. When the latter scheme is used, the cell sequence is retained at the output of the Abacus switch     

A general-purpose processor-per-pixel analog SIMD vision chip

A smart-sensor VLSI circuit suitable for focal-plane low-level image processing applications is presented. The architecture of the device is based on a fine-grain software-programmable SIMD processor array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analog microprocessor concept. This allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21 /spl times/ 21 vision chip is fabricated in a 0.6 /spl mu/m CMOS technology and achieves a cell size of 98.6 /spl mu/m /spl times/ 98.6 /spl mu/m. It executes over 1.1 giga instructions per second (GIPS) while dissipating under 40 mW of power. The architecture, circuit design and experimental results are presented in this paper.     

Approximate analysis of a multi-plane and multi-phase Banyan ATMswitch

An approximate analysis of a multi-plane and multi-phase Banyan ATM switch with both input and output buffering is presented. The approach gives a reasonable estimate of throughput and input queueing delay, and can be refined to give more accurate results     

Design and analysis of a large-scale multicast output buffered ATMswitch

Proposes and analyzes a recursive modular architecture for implementing a large-scale multicast output buffered ATM switch (MOBAS). A multicast knockout principle, an extension of the generalized knockout principle, is applied in constructing the MOBAS in order to reduce the hardware complexity (e.g., the number of switch elements and interconnection wires) by almost one order of magnitude. In the proposed switch architecture, four major functions of designing a multicast switch: cell replication, cell routing, cell contention resolution, and cell addressing, are all performed distributively so that a large switch size is achievable. The architecture of the MOBAS has a regular and uniform structure and, thus, has the advantages of: (1) easy expansion due to the modular structure, (2) high integration density for VLSI implementation, (3) relaxed synchronization for data and clock signals, and (4) building the center switch fabric (i.e., the multicast grouping network) with a single type of chip. A two-stage structure of the multicast output buffered ATM switch (MOBAS) is described. The performance of the switch fabric in cell loss probability is analyzed, and the numerical results are shown. The authors show that a switch designed to meet the performance requirement for unicast calls will also satisfy multicast calls' performance. A 16×16 ATM crosspoint switch chip based on the proposed architecture has been implemented using CMOS 2-μm technology and tested to operate correctly     

Three-dimensional switchbox multiplexing in emerging 3D-FPGAs to reduce chip footprint and improve TSV usage

Three-dimensional integration technology is proposed to break down long wires and increase integration level of emerging complex designs. However, efficiency of this technology heavily depends on the usage of Through-Silicon Vias. TSVs are key solutions for cooling the 3D-chips but they occupy considerable silicon area. Therefore, reducing the number of required TSVs in routing step is very critical in 3D-chips. In this paper, a TSV multiplexing approach is proposed to reduce the number of required routing TSV. We proposed two multiplexed 3D-switchbox architectures. In the first architecture, the TSVs inside the switchboxes are multiplexed while in the second architecture, TSVs are multiplexed between the switchboxes. Moreover, a routing algorithm is suggested to route the FPGA using the multiplexed switchboxes to evaluate the proposed architectures. Experimental results show that the presented architectures and algorithms reduce the number of used TSVs by 64.58% and 71.27% on average for the first and second architectures respectively, in cost of a negligible overheads in total wire length and auxiliary switches.     

Analytical model of round-robin scheduling for a geostationary satellite system

Round-robin scheduling is commonly employed in time-division multiple-access based medium access control protocols, to provide users with equitable access to a shared channel. The letter presents an analytical model to evaluate the mean end-to-end delay of packets traversing a geostationary satellite link with a round-robin free assignment scheduling strategy and Poisson source traffic. It is shown that the model can accurately predict the end-to-end delay performance of a round-robin scheduling satellite system.     

Fair scheduling with tunable latency: a round-robin approach

Weighted fair queueing (WFQ)-based packet scheduling schemes require processing at line speeds for tag computation and tag sorting. This requirement presents a bottleneck for their implementation at high transmission speeds. We propose an alternative and lower complexity approach to packet scheduling, based on modifications of the classical round-robin scheduler. Contrary to conventional belief, we show that appropriate modifications of the weighted round-robin (WRR) service discipline can, in fact, provide tight fairness properties and efficient delay guarantees to multiple sessions. Two such modifications are described: 1) list-based round robin, in which the server visits different sessions according to a precomputed list which is designed to obtain the desirable scheduling properties; 2) multiclass round robin, a version of hierarchical round robin with controls designed for good scheduling properties. The schemes considered are compared with well-known WFQ schemes and with deficit round robin (a credit-based WRR), on the basis of desirable properties such as bandwidth guarantees, fairness in excess bandwidth sharing, worst-case fairness, and efficiency of latency (delay guarantee) tuning. The scheduling schemes proposed and analyzed here operate with fixed packet sizes, and hence can be used in applications such as cell scheduling in ATM networks, time-slot scheduling on wireless links as in GPRS air interface, etc. A credit-based extension of the proposed schemes to handle variable packet sizes is also possible.     

Achieving round-robin access in controller area networks

Because of their low implementation costs, optimum responsiveness, and widespread availability, controller area networks (CANS) are being used more and more today to support communications in real-time systems. However, under heavy traffic conditions the CAN access protocol may exhibit a quite unfair behavior, in particular, when the control applications require the same quality of service to be ensured to a number of different objects. In this paper, a new technique is proposed which is based on CAN and introduces few changes to the original protocol. Such a solution is able to ensure a very fair behavior-which resembles the one obtained in token-based networks-while maintaining, at the same time, the reduced access delays typical of CAN when operating in low traffic conditions. Furthermore, it preserves an optimum degree of compatibility with the existing devices and applications based on CAN.     

Dynamic weighted cell multiplexing method for real-time traffic inATM

A new cell multiplexing algorithm is proposed to satisfy the service requirements of real-time traffic in ATM networks. The proposed algorithm is capable of assigning higher weights to real-time traffic than to non-real-time traffic, thereby guaranteeing the quality of service of real-time traffic. Simulation results show that the proposed algorithm has better performance than other cell multiplexing algorithms in terms of the mean delay time and the maximum queue length     

A file system for a general-purpose time-sharing environment

The file system for the Michigan terminal system (MTS) is described. MTS is a general-purpose multiprogramming multiprocessing paged time-sharing system for the IBM 360/67 and 370/168 developed at the University of Michigan, Ann Arbor. First, an overview of some of the external facilities provided to the users of files is presented; then some of the internal design philosophy and corresponding implementation strategy for the file system are discussed. Particular emphasis is placed on how the sharing of files is accomplished, both from the user's point of view and the system's point of view. A retrospective judgment of some of the strengths and weaknesses of the MTS file system is given. Finally, an appendix details the allowable concurrent usage of files and the algorithm used for file deadlock detection in MTS.     

Use of a time-shared general-purpose file-handling system in hospital research

Techniques in automated data-handling for medical research and patient-care purposes are being investigated using a conversational timeshared computer system. This paper covers the initial design considerations, implementation experience, and user reaction with the prototype set of on-line, multiple-access, general-purpose information storage and retrieval programs. This system is designed to pemit hospital personnel (without the need for special assistance or any direct intervention by trained computer programmers) to define and establish private data files, to enter or change moderately large volumes of English text or coded data, and to retrieve and manipulate selected output information. Hospital staffs, from remote terminals, have been using this system on an operational basis for more than a year. The development and implementation of the system is being carried out by Bolt Beranek and Newman Inc., and the Massachusetts General Hospital, under the support of the National Institutes of Health.     

Analogue multiplexing using a digital technique

A digital technique of multiplexing analogue signals is described whereby improved isolation between channels and negligible equivalent-channel `on? resistance is achieved. It is also suggested that the proposed method may find application in analogue?digital conversion     

Synchronizing and multiplexing in a digital communications network

A concept of a totally digital communications network is described in which all signals are converted into digital form and remain so as they are multiplexed, switched, and transmitted. To permit time-division techniques for such network processing, and thus realize significant economic advantages, the digital signals must be either generated in synchronism or brought into synchronism. While the switching portion of this network is not yet in service, some of the transmission network already exists and the evolution toward a digital transmission hierarchy is well underway. The hierarchy consists of 1) terminals which convert analog Signals into digital form suitable for transmission, 2) transmission facilities which are available at various capacities, and 3) multiplexers which can derive several lower capacity digital facilities from a single high-capacity system. Such a network, when complete, can also disseminate time and frequency for other uses with the same accuracy as required by the network. The network requires that the relative phase difference between any two signals must be bounded, which means exact matching of the long-term average frequency throughout the network. Signal-processing time and variations in propagation velocity in various media-cable, radio, waveguide-control the short-term accuracy. This network can thus provide time-and-frequency information proportional to the observation time. Available techniques that can achieve such accuracy for the network are discussed.     

Uncertainty analysis of the CISPR/a radiated emission round-robin test results

A large round-robin test (RRT) was carried out to obtain quantitative information about the uncertainties that play a role in an International Electrotechnical Commission/International Special Committee on Radio Interference (IEC/CISPR) radiated emission test in the frequency range 30 to 300 MHz. Two different equipment under tests (EUTs) allowed us to distinguish between the measurement instrumentation and the EUT-induced uncertainties, a subset of the standards compliance uncertainties. This paper presents the rationale behind the various RRT-measurements, the way the ancillary equipment was continuously checked, the measurement results and the results of their statistical analysis. The test sites included open-area test-sites, semi-anechoic rooms and fully anechoic rooms. A major conclusion is that measurement instrumentation uncertainty considerations alone cannot explain the uncertainty relevant in an actual CISPR radiated emission compliance test.     

Angular multiplexing for multichannel communication in a single fiber

A concept of angular multiplexing of several communication channels in a relatively short step-index fiber is described. The angular dependence of the outgoing light flux and the temporal impulse response are calculated for slab waveguides and round fibers in terms of the fiber's length and the excitation conditions. Calculations of the inpulse response in the presence of mode coupling are based on a simple model which is found to be adequate for short fibers. Crosstalk levels are calculated by integrating the flux over the aperture of the detectors. Measurements of angular flux distribution, temporal impulse response, and crosstalk levels agree with theoretical prediction and validate the proposed concepts. To increase light levels, parallel excitation of each channel by several light sources is suggested and tested. Also, light collection efficiency is increased by employing lenses and annular mirrors to deflect and focus the light from each channel to small-area detectors. Given a 25 m long fiber with a coupling constant of 10^-5rad²/m, it is possible to multiplex four channels with cross-talk of about -25 dB and information rates ranging from 10⁹bits/s to 10¹⁰bits/s for each channel.     

Blocking in a system on a chip

With more and larger functions being implemented on a single piece of silicon, true systems on a chip are being created. At the physical level, this integration derives from progress in process technology. But from the circuit designers' viewpoint, tools and methods are less help than they might be. In effect, to construct a system on a chip means more than the integration of millions of transistors. A set of complicated and rapidly evolving technologies and standards for telecommunications, multimedia, and PCs must be mastered, too. Also, the software content of most electronic systems has been growing for several years and now often accounts for a major part of the final product and hence of the design effort. Since a system on a chip is a system, a design methodology for generating such complex ICs will frequently have to address the software as well as hardware needs. Further more, as the size and complexity of chips has grown, so too has the task of verification. Verifying the design of a chip containing a million gates of logic presents a formidable challenge of its own. The complexity of large designs calls for a shift in the design paradigm to one based on reusable, high-level building blocks. Currently, most functional blocks are created by hand and are seldom used again. Reusable blocks, though, are not enough. To deliver on the promise of more productivity and less time to market, designers need reinforcements-a methodology and tools with which to integrate the blocks efficiently, plus standards that support the creation of reusable blocks, their exchange, and their integration     

Code-division multiplexing of a sensor channel: a softwareimplementation

This paper demonstrates the use of software radio techniques in the context of sensing, rather than communications. It describes code-division multiplexing (CDMA) and time-division multiplexing (TDMA) of a receiver channel in an electric field sensing system. The only hardware used is a front-end gain stage consisting of two opamps and a microcontroller. The modulation and demodulation operations are implemented entirely in the microcontroller software. Multiple coded waveforms are transmitted simultaneously, and induce a combined signal on a single receive electrode. The combined signal, after passing through a single analog front end terminating in an analog-to-digital converter, is separated into the four original component signals by a software demodulation operation. The signal-to-noise ratio (SNR) achieved by the code-division multiplexed system given a fixed measurement time is compared to the SNR achieved by a time-division multiplexed implementation given the same total measurement time. The paper also compares the scaling of TDMA and CDMA performance with the number of transmitted channels and the number of demodulated channels     

Optical amplifiers-light boosters in a chip

One potential way of building transmission systems able to accommodate capacity upgrades is to use optical amplifiers. These devices simply amplify the incoming optical signal. They are insensitive to the transmission bit rate and data format, have a broad optical bandwidth, and, in principle, pass signals in either direction. Optical amplifiers are thus highly flexible devices, potentially able to accommodate a wide range of improvements in the transmission system including increases in the bit rate, frequency-division multiplexing and coherent transmission. The author describes the construction of optical amplifiers and their operation including packaging, gain control and fault location. Their use in submarine links between the UK and mainland Europe is also discussed     

CMOS prototype vision chip with digital pixel structure for grey level image segmentation by means of thresholding and time multiplexing

In this article, a CMOS prototype vision chip with digital pixel structure for grey level image segmentation by means of thresholding and time multiplexing is presented. This approach splits scenes into m frames (one frame per grey level interval). One advantage about this design is that an analogue to digital converter is not required. Moreover, image acquisition and segmentation are performed at the same time by pixels that work simultaneously with each other. The performance from each pixel deals with a maximum quantum efficiency of 0.65, pixel size of 132 μm × 176 μm, fill factor of 0.78%, dark current of 15 mV/s, power dissipation per frame of 341 μW, minimum exposure time of 28.6 μs, maximum exposure time of 1.9 ms, random noise of 3 mV, optical dynamic range of 51 dB and majority of cells with 0–3% of mismatch. Scene decomposition into 256 images occurs in 30.5 ms with white illumination of 650 Lx.     

Mirrors on a chip

The design, development, and performance of the digital micromirror device (DMD), a spatial light modulator for projection displays, are examined. The DMD covers each memory cell of a CMOS static RAM with a movable micromirror. Electrostatic forces contingent on the data in the cell tilt the mirror either on or off, modulating the light incident on its surface. Light reflected from any on-mirrors passes through a projection lens and creates images on a large screen. Light from the remaining off-mirrors is reflected away from the projection lens and trapped. The standard-resolution version of the DMD corresponds to the National Television System Committee (NTSC) or Phase Alternation Line (PAL) standard. It is a chip about 2.3 cm² covered by 442368 movable mirrors, each 16 μm on a side