A Built-in Self-Test Scheme for Memory Interfaces Timing Test and Measurement

This paper presents a Built-In Self-Test (BIST) technique to test the setup and hold times of memory interface circuitry. The BIST scheme generates data and clock using an on-chip pattern generator. The relative timing difference between data and clock is controlled using a cycle-by-cycle control method for testing. Two test methods of static and dynamic modes have been presented to measure the timing difference and then are used to specify the setup and hold times. The static mode is mainly used to detect pass or fail for timing specifications, and the dynamic mode is devised to measure the amount of timing mismatches and thus detect timing margin degradations due to the timing delay mismatches. Using these two test modes, the BIST scheme obtains test results with low frequency signals, which are compatible with low performance testers. The test chip including the BIST scheme has been fabricated with a commercial 0.18-μm CMOS process. The chip measurement results are shown to validate the testability of the BIST scheme for the setup and hold times of memory devices.     

基于AT89C2051的检测系统信号采样及数据提取的设计

在检测系统中,常采用多路数据分时复用的串行传输方式,并需要将其中的数据提取出来,若采用硬件电路,实现比较复杂。提出了将串行信号中鉴别出来的正脉冲信号送至INT0,利用AT89C2051单片机的外部中断0并通过程序延时来控制采样点的位置,在每个脉冲信号的中间位置采样,达到提取数据的目的。     

基于TMS320C6711的Camera Link相机控制的实现

在分析了面阵CCD相机1M30的Camera Link协议接口特点的基础上,设计了一种具有较强通用性的DSP系统对Camera Link相机的控制方案.采用定时器和软件编程等手段,解决了DSP芯片TMS320C6711的多通道缓存串口(MCBSP)与1M30间异步串行通信的传输速率及数据格式问题,成功设置相机参数;研究了在串行数据中产生帧同步接收信号(FSR)的可行性及失败原因.借助定时器产生的周期性脉冲信号及中断,使MCBSP可靠地接收相机反馈信息;根据相机曝光时序特点,用程序实现对相机的正常曝光控制.     

A complete 400-Mb/s burst-mode data OEIC receiver

A fully integrated burst-mode GaAs MESFET optoelectronic integrated circuit (OEIC) receiver, 215 mil×109 mil, that has been designed and implemented for point-to-point data links for application as a phased-array antenna controller is described. The chip provides a low-cost means for passing 400-Mb/s antenna control information using fiber optics with a very low bit-error rate (BER). Approximately 350 source-coupled FET logic gates are present on the chip. A new data coding and timing recovery scheme that is highly tolerant to jitter over a wide bandwidth has been developed. The OEIC uses an on-chip metal-semiconductor-metal (MSM) photodiode with 0.12-A/W responsivity measured at 780 nm and was fabricated in a 1.0-mm GaAs MESFET manufacturing technology. The low capacitance semi-insulating GaAs substrate minimizes the coupling between analog and digital circuitry. The circuit operates from a single 5-V supply, consumes 1 W of power, and provides an 8-b CMOS output bus together with various utility flags. Optical sensitivity is estimated at -20 dBm for 10^-14 BER     

Measurement and modeling of on-chip transmission line effects in a400 MHz microprocessor

On-chip interconnect delays are becoming an increasingly important factor for high-performance microprocessors. Consequently, critical on-chip wiring must be carefully optimized to reduce and control interconnect delays, and accurate interconnect modeling has become more important. This paper shows the importance of including transmission line effects in interconnect modeling of the on-chip clock distribution of a 400 MHz CMOS microprocessor. Measurements of clock waveforms on the microprocessor showing 30 ps skew were made using an electron beam prober. Waveforms from a test chip are also shown to demonstrate the importance of transmission line effects     

An Externally Powered, Multichannel, Implantable Stimulator for Versatile Control of Paralyzed Muscle

Through the use of semicustom integrated circuit technology, an implantable muscle stimulator has been developed. The unit is small, lightweight, has low power consumption, and is intended for permanent usage. The stimulator circuitry is externally controlled and powered by a single encoded radio frequency carrier. Up to eight independently controlled stimulus output channels are provided, with output channel selection, stimulus pulse width, and stimulus pulse frequency under external control. A constant current biphasic stimulus pulse is used, in which the stimulus current amplitude can be preset by a single resistor value. The stimulator circuitry has been implemented in thick film hybrid form, and has undergone laboratory evaluation for 48 months.     

A custom-designed receiver-stimulator chip for an advancedmultiple-channel hearing prosthesis

A receiver-stimulator integrated circuit for an advanced multiple-channel cochlear implant was custom designed and fabricated successfully, using a 3-μm CMOS process with two layers of metal. The chip contains nearly all of the implant electronics, including a data receiver, digital-to-analog converter, three stimulus current generators and timing controllers, 20 output stages, and an outward telemetry subsystem. The measured power consumption of the chip when quiescent, with supply voltage of the receiver stimulator (V_DD) at 12 V and while receiving unmodulated RF carrier, was 6.8 mW. The implant's total power consumption when stimulating under worst-case conditions (three stimuli being generated at the maximum rate with maximum current levels and durations) was 45 mW     

An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology

An active solution is proposed to overcome the uncertainty and fluctuation of the device parameters in nanotechnology SRAM. The proposed scheme is composed of sensing blocks, analysis blocks and control blocks. An on-chip timer, temperature sensor, substrate noise detector, and leakage current monitor are used to monitor internal status of chip during operation. From the sensed data, internal supply voltage, internal timing margin from decoding to sensing time, substrate noise from digital area, and low voltage level of wordline are controlled. A 512-kb test SRAM chip, fabricated with an 80-nm double stacked cell technology, shows that average power consumption is reduced by 9% and the standard deviation decreases by 58%.     

An implantable wireless bidirectional communication microstimulator for neuromuscular stimulation

This paper presents the integrated circuit design for a wireless bidirectional transmission microstimulator. This implantable device is composed of an internal radio-frequency (RF) front-end circuit, a control circuit, a stimulator, and an on-chip transmitter. A 2-MHz amplitude-shift keying modulated signal, including the power and data necessary for the implantable device, is received, and a stable 3-V dc voltage and digital data will be extracted to further execute neuromuscular stimulation. The current-mode microstimulator can produce a bidirectional output current with 8-bit resolution for stimulation. The maximum stimulation current is 1 mA while the stimulation frequency is from 20 Hz to 2 kHz and the pulsewidth of stimulation current is from 150 to 500 /spl mu/s. Furthermore, the system can acquire the biological sensing signal by means of an on-chip transmitter. Most of the signal processing circuits have been designed with low-power schemes to reduce the power consumption, and the performance is also conformed to the requirements of the microstimulator. All of the circuits except for the RF link are combined in a single chip and implemented in TSMC 0.35-/spl mu/m 2P4M standard CMOS process.     

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications

An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm/sup 2/ 16-Mb embedded DRAM macro is fabricated in 0.13 /spl mu/m logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36 % for an RC delay can be reduced to 3.8% by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-/spl mu/W data retention power is realized by using the PDDR mode, which is 5% of conventional schemes.     

基于双重调制技术的可见光通信系统研究

LED调制带宽制约着可见光通信(VLC) 系统的数据传输速率。为此,提出一种基于双重调制技术COB(chip on board)封装 的LED灯具,通过实现16级脉冲振幅 调制(PAM),将系统数据传输速率提升4倍;结合脉冲宽度调制(PWM)技术 进行调光,同时兼顾室内的照明及通信。采用Matlab软件模拟仿真视频传输试 验。结果表明,在相同信噪比(SNR)的情况下,基于双重 调制技术的VLC系统的误码率(BER)比传统使用开关键控(OOK)调控技术系 统的BER更低。本文系统在不增加器件带宽前提下,成倍提高了无线通信的 质量与 数据传输速率;从照明与通信的角度优化了VLC系统的信源,具有广阔的 应用前景。     

Simultaneous transmission of MAP IE and data for minimizing MAC overhead in the IEEE 802.16e OFDMA systems

An advanced MAP transmission scheme for improving Media Access Control(MAC) overhead in the IEEE 802.16e systems is proposed. In the IEEE 802.16e system, when a Base Station(BS) broadcasts a MAP message, which is a control message about scheduling information, it applies a robust Modulation and Coding Scheme(MCS) level and allocates a large amount of radio resources, which induce a huge MAP overhead. Our proposed scheme utilizes piggybacked MAP IEs, in which control messages are concatenated with data packets and transmitted with the MCS level applied to data transmission. Due to the fact that the rate at which data is transmitted is generally higher than the rate at which broadcasting messages are transmitted, the proposed scheme can increase average data rate of a MAP transmission and consequently reduce the amount of resources allocated to the MAP transmission. Numerical analysis and simulations are presented to show that the MAP overhead is critical to system performance and can be improved by the proposed scheme.     

Selected mapping without side information for PAPR reduction in OFDM

Selected mapping (SLM) is a technique used to reduce the peak-to-average power ratio (PAPR) in orthogonal frequency-division multiplexing (OFDM) systems. SLM requires the transmission of several side information bits for each data block, which results in some data rate loss. These bits must generally be channel-encoded because they are particularly critical to the error performance of the system. This increases the system complexity and transmission delay, and decreases the data rate even further. In this paper, we propose a novel SLM method for which no side information needs to be sent. By considering the example of several OFDM systems using either QPSK or 16- QAM modulation, we show that the proposed method performs very well both in terms of PAPR reduction and bit error rate at the receiver output provided that the number of subcarriers is large enough.     

基于低信息泄露协商算法的无线信道密钥生成方案

针对无线信道生成密钥方法在信息协商中的信息泄露问题,提出了低信息泄露Cascade算法。通过构造传统Cascade协商过程的密钥协商过程矩阵,推导了合法用户所得密钥中安全的信息量,改进了Cascade算法;结合符号定时同步预处理以及高精度参数估计得到了一个完整的密钥生成方案。基于实测数据的分析结果表明,符号定时同步预处理能有效降低初始密钥不一致率;在协商成功率、密钥生成速率、密钥随机性、安全性等方面,低信息泄露Cascade协商算法与传统Cascade算法相比综合性能更优。     

VLSI implementation of a variable-length pipeline scheme fordata-driven processors

A VLSI-oriented variable-length pipeline structure for data-driven processors is presented. Ordinary inline pipelines have the problem of minimizing the average total processing time through the pipeline, since subdivision of a function along the pipeline is usually optimized for the most complex operations in spite of the fact that simpler operations need fewer stages. As a solution to this problem, a variable-length pipeline scheme in which data go through only the necessary stages according to information contained within is proposed. The scheme has been implemented on a test chip to verify performance. The chip demonstrated a minimum fall-through time (data transmission time from input to output) of 14.4 ns and a data transmission rate in the pipeline of 59 megaword/s (that is, 1/16.9 ns) as a first-in first-out (FIFO) store. By modifying the data transfer control and allocating the processing functions corresponding to the data interval of 16.9 ns, this scheme is applicable as a high-performance processing unit for data-driven processors     

Analog signal generator for BIST of wideband IF signals bandpass sigma-delta modulator

This paper presents improvements in generation of wideband and high dynamic range analog signal for area-efficient MADBIST, especially for the on-chip testing of wireless communication IF digitizing sigma-delta modulator chip. Via increasing the order of the one-bit bandpass sigma-delta modulation algorithm up to 12 and using finite repetitious bitstream approximating scheme, it can achieve great improvements in signal bandwidth instead of purity at the cost of very little hardware overhead. Another contribution in this work is to provide the theoretical analysis of the reconstructed signal degradation due to harmonic distortion and clock jitter. Such on-chip analog stimulus generation scheme is especially fit for IF digitizing bandpass sigma-delta modulator chip's production-time testing and in-the-field diagnostics. The technique can also be extended to mixed-signal communication SoC built-in-self-test.     

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a program along with compressed test data into the processor's on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the other components of the SOC to test them. The program itself is very simple and compact, and the decompression is done very rapidly, hence this approach reduces both the amount of data that must be stored on the tester and reduces the test time. Moreover, it enables at-speed scan shifting even with a slow tester (i.e., a tester whose maximum clock rate is slower than the SOC's normal operating clock rate). A procedure is described for converting a set of test cubes (i.e., test vectors where the unspecified inputs are left as X's) into a compressed form. A program that can be run on an embedded processor is then given for decompressing the test cubes and applying them to scan chains on the chip. Experimental results indicate a significant amount of compression can be achieved resulting in less data that must be stored on the tester (i.e., smaller tester memory requirement) and less time to transfer the test data from the tester to the chip.     

A novel compact circuit for 4-PAM energy-efficient high speed interconnect data transmission and reception

Transmission of signals, whether on-chip or off-chip, places severe constraints on timing and extracts a large price in energy. New silicon device technologies, such as back-plane CMOS, provide a programmable and adaptable threshold voltage as an additional tool that can be used for low power design. We show that one particularly desirable use of this freedom is energy-efficient high-speed transmission across long interconnects using multi-valued encoding. Our multi-valued CMOS circuits take advantage of the threshold voltage control of the transistors, by using the signal-voltage-to-threshold-voltage span, in order to make area-efficient implementations of 4-PAM (pulse amplitude modulation) transceivers operating at high speed. In a comparison of a variety of published technologies, for signal transmission with interconnects of 10-15 mm length, we show up to 50% improvement in energy for on-chip signal transmission over binary encoding together with higher limits for operating speeds without a penalty in circuit noise margin.     

A high-speed sample-and-hold circuit based on CMOS transmission lines

We introduce the design of a high-speed sample-and-hold circuit (SHC) based on spatial sampling with CMOS transmission lines (TLs). Signal propagation analysis shows that periodically loaded CMOS TLs exhibit filter properties, which cause attenuation and deformation of signal pulses. Nevertheless, the dispersion effects on clock pulse propagation are minimal since clock lines are short, much shorter than the meandered input-signal line. Design considerations on clock pulse generator, sampling switches, and charge amplifiers are presented. Compared with other CMOS approaches, the proposed SHC generates clock pulses on chip and avoids clock jitter difficulties. The SHC is implemented in a 0.13 μm digital CMOS process with standard on-chip coplanar waveguides (CPW) as signal and clock pulse propagation TLs, silicon N-type field effect transistors (NFET) as sampling switches, and high-frequency charge amplifiers for charge amplification. Clock pulse signals of ~50 ps width with ~17 ps fall edge are generated on-chip. Simulation analysis with Cadence Spectre shows that a sampling rate of 20 Giga-sample/s with a 25 dB spurious free dynamic range (SFDR) can be achieved. With shorter clock pulses, both sampling rate and SFDR can be improved in future design.     

A 16-kbit block addressed charge-coupled memory device

This paper describes the design and performance of a 16- kbit charge-coupled serial memory device. The memory is organized in four blocks of 4 kbits each with on-chip decoding and is mounted in a 16-pin ceramic dual-in-line hermetic package. Each 4-kbit block is organized as a serial-parallel-serial (SPS) array. Operated at a data rate of 1 MHz the mean access time is 2 ms and the on-chip power dissipation is calculated to be 1.5 µW/bit with another 0.5 µW/bit being required in off-chip clock drivers. The maximum designed output data rate is 10 MHz. Compared to the serpentine and loop organized memory charge-coupled device (CCD), the SPS organization has the advantages of lower power dissipation, greater tolerance to process parameter variations, and higher output data rate. All inputs and outputs are TTL compatible. Write/recirculate control is provided on the chip as well as two-dimensional decoding to permit memory matrix organization with X, Y chip select control. All the on-chip peripheral circuits use dynamic MOS circuitry to minimize power consumption. The charge sensing on the chip is achieved with balanced regenerative sense amplifiers. The memory array uses the three-phase three-level polysilicon electrode structure, and the chip is fabricated using an MOS n-channel polysilicon gate process with self-aligned source, drain, and channel stop.