基于BCB的薄膜多层基板在毫米波T/R组件中的应用

基于BCB的薄膜多层基板具有优异的高频特性,是毫米波频段多芯片组件集成封装的重要途径。研究了BCB薄膜多层基板在Ka波段相控阵雷达T/R组件中应用的可行性,首先与LTCC基板对比验证了BCB微带线的传输特性,然后研制了功率分配/合成器、穿墙过渡等关键微波无源电路,最后设计了八通道的无源组件进行微波性能测试评估,结果表明基于BCB的薄膜多层基板能够满足应用需要。     

Scalability and pilot operation in solar cells of CuInSe2 and their alloys

The compound Cu(Ga,In)Se₂ (CIGS), and related compounds, have demonstrated their high potential for high-efficiency thin-film solar cells up to levels approaching 18%. It is expected that this quality can be further improved by optimizing process conditions and combining the CIGS with other group I, III and VI elements. Other material combinations are under development. Several companies and research institutes are developing CIGS-based technology with the aim of low cost/high volume production. The key process is a scalable technology to fabricate highest quality CIGS films on a large area with high throughput and process yield. The Centre for Solar Energy and Hydrogen Research (ZSW) and the University of Stuttgart (IPE) are working together on CIS technology. On the module basis ZSW is negotiating with private companies to commercialize module technology. These activities are compared with others worldwide. With the aim of developing relevant high-volume fabrication technologies, all laboratory deposition techniques that have proven highest device performance are applied also on the module level to prevent physical and chemical effects that could limit device performance. All film deposition techniques are developed for high-vacuum in-line fabrication on a large area except for the buffer layer of CdS, and monolithic integration is realized by patterning steps. Modules are prepared on substrate areas of 10×10 up to 30×30 cm². Actual results of modules of these sizes are 14% and 10%, respectively. Estimations of fabrication costs with increasing fabrication volume show that it is possible to produce CIGS modules at costs well below US$1 W⁻¹_p. © 1998 John Wiley & Sons, Ltd.     

系统模块(SiP)和三维封装(3D)在移动通讯中的应用

电子封装业界正遭受着前所未有的来自手机和其他移动通讯终端设备挑战。在这一领域里,IC封装的关键是尺寸微型化,缩减成本和市场时机。这一挑战的背后隐含着手机技术发展的两大趋势:系统模块化和日益增长的复杂性及功能。越来越多的功能正在被组合到手机上即PDA、MP3、照相机、互联网等等。功能的增加需要靠模块化来实现,而模块化又促进了更多功能的组合。同时,模块化使得移动通讯终端设备得以微型化、降低成本和缩短设计周期。业界越来越多地感受到整体射频模块和通讯模块解决方案的必要性。这些整体模块把手机设计师从电路设计的细节中解脱出来,从而能专著于高层的手机应用和系统的设计。为了满足上诉移动通讯产品的苛刻要求,大量的新兴电子封装技术和封装产品应运而生。最引人注目的例子在于对系统模块穴SiP雪和三维穴3D雪封装的重点资金和技术投入。这两项先进封装技术有着各自不同的特征和应用范围。总体介绍先进封装技术在移动通讯中的应用,重点讨论电子封装材料和工艺所面临的挑战和最新发展趋势。对移动通讯带来的新一轮集成化及其所产生的潜在供应链问题也做了适当的讨论。     

Substrates,contacts and monolithic integration

Substrates and contacts play a critical role in thin-film solar cell device and module performance. They influence light trapping, film growth, impurity levels, doping, stability, yield and laser scribing for monolithic integration. The substrate is also a major cost factor, often accounting for the largest component of the module cost. The interaction between the substrates or contacts with the semiconductor layers can also limit the range of the subsequent semiconductor layer processing parameters. The panel and audience discussed these factors in relation to fabrication, performance and characterization of today's thin-film solar cells and modules. © 1997 John Wiley & Sons, Ltd.     

Polycrystalline silicon thin-film solar cells: The future for photovoltaics?

Based on performance, material availability, consumer acceptance, life expectancy, environmental considerations and the potential for low cost, thin-film polycrystalline silicon solar cells are well placed to have a significant impact in the future. of key importance will be the achievement of performance targets, because module efficiencies of at least 15% are probably necessary in the long term for photovoltaics to have a significant impact in grid-connected applications. Strategies for achieving these performance levels with mediocre material quality and only moderate surface passivation and light trapping are presented. the challenges associated with the supporting substrate choice and layer depostion techniques and structures are discussed and the psesent practices reviewed. Important considerations include device performance, cost, throughput, device area and simplicity of fabrication and operation. Promising efficiencies in the vicinity of 15% have already been demonstrated using a number of different crystalline silicon layer-formation techniques. Novel device structures based on incorporation of narrow bandgap materials (Si/Ge alloys) or defect layers, quantum wells and the impurity photovoltaic effect are considered, with particular emphasis given to approaches that compensate for the current loss in thin-film cells. It appears increasingly likely that polycrystalline silicon thin-film solar cells will have an impact on the development of photovoltaics in the future and may in fact provide the means for the substantial cost reductions necessary for significant penetration into utility markets.     

A Lumped-Element Circulator without Crossovers (Short Papers)

It is proposed to construct a simple "crossoverless" Iumped-element circulator, which can be made without sophisticated thin-film processing. The circulator can be described by a "delta connected" equivalent circuit. A simple capacitor arrangement can be used to influence the three eigenvalue phases of the circulator independently, thus permitting this circulator to be maximized systematically. A set of computer-generated eigenvalues gives insight into the behavior of the device under varying operating conditions. Preliminary measurements using a very simple pattern on a 0.650-in-diam ferrite substrate show a 20-dB bandwidth of 10 percent and an insertion loss < 1 dB (0.3 dB/min) at L band.     

Design and development of optoelectronic mixed signal system-on-package (SOP)

This paper describes the design and development of a 2.5-Gb/s optical transceiver module as a mixed signal SOP for access networks. The module development consists of concurrent design of an optoelectronic package optimizing optical, electrical, thermal, mechanical functions and optical subassembly and RFICs housed in a chip-on-board package. The optical subassembly (OSA) consists of laser and photodiode assembled on a silicon substrate. The transmit and the receiver sections are combined into a single fiber through a polymer coupler on silicon. The splitter between the transmit and receive section is realized using a polymer waveguide. The electronic ICs are assembled on a multilayer organic substrate. The package design includes optical coupling design, impedance matched transmission line design for RF signals, electrical layout design for mixed signals and thermal design for the package. The module is housed in a plastic molded nonhermetic package to achieve low cost packaging. The assembly is completed using passive alignment of optical devices and attachment of electronic devices using adhesives. In this paper, we present the details of the component design and the development of packaging process methods to achieve the design specifications, test results and process guidelines for assembly and integration.     

Flip-chip packaging solution for CMOS image sensor device

Chip scaled opto-electronic packaging is introduced as a cost and size effective packaging solution for mobile phone with built in camera. The chip scaled assembly includes gold bumped CMOS image sensor device and its flip-chip bonding on substrate using the anisotropic conductive material. Two types of flip-chip module were designed to have flip-chip on flex and flip-chip on glass. It is shown that well controlled bumping process of thin film deposition and wet etching gives no damage to image sensing surface during the deposition and stripping of metal film. As results, smart and high degree miniaturized image sensor module is actualized for mobile phone and the reliability test results proved the robustness of module structure having flip-chip. Solder bumping was also reviewed and successfully introduced to verify the alternative of image sensor bumping.     

户内新型高密度LED显示器件及显示屏的研究

集成电路具有密度高、引线短、外部接线少、体积小、重量轻、成本低、使用方便等特点,提高了电子设备的可靠性和灵活性,在性能上也优于分立元件。采用集成化方式生产的LED显示器件,采用金属外壳封装工艺,很好地解决了集成模块的散热和均热问题;采用COB生产工艺,像素密度可超过25万点／平方米;集成化封装工艺使LED芯片得到了良好的保护;表面黑化处理工艺使整屏的显示效果更好。采用该新型器件,并结合逐点校正技术制造的显示屏,将校正数据存储在模组中,上电后控制器自动读回校正数据,对画面进行校正处理。很好地消除了模块效应．可以得到完美的显示效果。     

A new concept of p-(n-)/p-(n ) thin-film epitaxial silicon wafers for MOS ULSI's that ensuresexcellent gate oxide integrity

A new concept of epitaxial silicon (Si) wafers (NC epi) in which p ^-(n^-) thin-film layers are grown on p^-(n^-) Czochralski (CZ)-Si substrates (substrate resistivity: approximately 10 Ω cm) is proposed for metal oxide semiconductor (MOS) ultra large-scale integrated circuits (ULSI's) as a starting material. A thickness of 0.3-1 μm for the epitaxial layer (p ^-/p^- structure) is shown to be sufficient for improving the gate oxide integrity for MOS-ULSI's. The epitaxial layer grown on Si substrate greatly reduces weak spots in the gate oxide layer by covering microdefects in the CZ-Si represented by the crystal originated particle (COP). The p^-/p^$thin-film epitaxial structure results in very controlled resistivity for the electrically active region in the device, which in turn results in a lower growth cost and higher feasibility for use in current ULSI's. The features of NC epi in combination with proximity gettering is presented. An application of NC epi in shallow-trench isolation processes is discussed, considering the retrograde-type well-tub. The amenability of epitaxial wafers to wafer enlargement (over 300 mm) is discussed to eliminate the bad effects of COP     

Characterization and modeling of Cu(In,Ga)(S,Se)2-based photovoltaic devices: A laboratory and industrial perspective

This contribution is a summary of a workshop convened to discuss the characterization and modeling of thin-film CuInSe₂(CIS)-based solar cells, 17-19 October 1993, in Estes Park, Colorado. the participants of the workshop are the authors of this paper. the subject matter was examined along four lines: device modeling, characterization, processing, and manufacturing issues. Fundamental numerical modeling has successfully guided device design efforts, including the design of variable band-gap absorbers. Quantitative analysis, however, has been compromised by incomplete data on fundamental material properties. Phenomenological modeling and device characterization have sucessfully contributed to the understanding of the device physics. Although classified as a heterojunction device, the forward-current recombination of the ZnO/CdS/CIS occurs almost exclusively in the space-charge with diode quality factors ranging from 1.2 to 1.7 for good devices. the next generation of device modeling must incorporate two- and three-dimensional effects. Recent fabrication work has focused on improving the CIS absorber and adding Ga and S to the matrix to increase its band-gap. A better understanding of the ternary's fundamental properties is required to support the modeling efforts. Control of Ga and S introduction and the resulting absorber band-gap profiles will facilitate the realization of optimized device designs. Inadequate understanding of fundamental device operation and process control at the laboratory level are amplified in the manufacturing environment. Modeling and characterization can identifv areas where corrective actions will result in improved performance and yield at the module level.     

基于LTCC 厚薄膜混合基板的Ka 波段T/ R 组件封装技术

收发组件的集成封装技术是毫米波二维有源相控阵领域应用研究的重点和难点。文中采用基于低温共烧陶瓷厚薄膜混合基板制造工艺技术,同时结合先进的微组装工艺,实现了Ka 波段八单元组件的高精度、高密度及气密封装;给出了收发组件的封装模型,通过仿真与实测对比着重分析了垂直互联、功率分配/ 合成网路及通道隔离的提升等关键技术,并测试了无源组件的微波性能。结果表明:该集成封装技术能够满足二维毫米波相控阵天线对T/ R 组件小型轻量化和高组装密度的技术要求。     

Amorphous-silicon/silicon-nitride thin-film transistors fabricatedby plasma-free (chemical vapor deposition) method

The application of chemical-vapor-deposited (CVD) amorphous-silicon and silicon-nitride films to active layers of thin-film transistors on a glass substrate is discussed. The maximum process temperature was 485°C. The maximum field-effect mobility and the typical on-off current ratio were more than 0.9 cm²/V-s and 10⁶, respectively. Advantages of applying the fully plasma-free CVD method in the amorphous-silicon thin-film transistor process are discussed     

Signal integrity characterization of microwave XFP ASIC BGA package realized on low-K liquid crystal polymer (LCP) substrate

With the development of low-K nanometer devices, the need for compatible packaging material is ever increasing. Liquid crystal polymer (LCP) is emerging as a promising material for RF, microwave, and millimeter-wave packaging. Its coefficient of thermal expansion can be matched to that of low-K die to ensure mechanical reliability. This paper, for the first time, characterizes the electrical performance of a wire bonded application-specific integrated circuit (ASIC) ball grid array (BGA) package based on LCP substrate technology for application in 10 Gb/s small form factor pluggable module (XFP) optical communication systems. Specifically, it compares the electrical performance of LCP to that of traditionally used FR4/spl I.bar/epoxy (FR-4) and Polyimide (PI) substrate materials. Findings show that at 10 GHz, insertion loss was decreased as much as 31% and 15% compared to FR-4 and PI, respectively. In particular, mode conversion was decreased by 66% and 42% compared to FR-4 and PI, respectively. Time delay was decreased by 10 and 4 ps compared to FR-4 and PI. No significant differences in power, ground coupling, and simultaneously switching output (SSO) noise at 10 GHz were observed. Based on the package structure used in this study, it was concluded that LCP offers superior electrical performance compared to FR/spl I.bar/4, PI, and is qualified as next generation substrate material for high data rate XFP BGA packaging.     

Saddle add-on metallization for RF-IC technology

A cost-effective add-on process module for reducing ohmic losses of radio-frequency (RF) inductors and interconnects in RF/BiCMOS and RF/CMOS technologies built on CMOS logic processes is proposed. The module is based on the local thickening of the top metal layer of the thin CMOS interconnects through copper (Cu) electroplating in selected areas. The combination of dense Cu-interconnects in the CMOS logic sections, of thick Cu top-level wiring through local Cu electroplating in the RF sections, and of aluminum (Al) capping of the bond pads provides an optimum tradeoff between packaging requirements, quality of passive components and interconnects, and cost. A special wet-etch process sequence for removal of the Cu-seed and adhesion films from the exposed top metal layer is described. A record quality factor of /spl sim/13 for a 10-nH inductor on a conventional 5-/spl Omega/-cm silicon substrate is demonstrated.     

Integrated RF architectures in fully-organic SOP technology

Future wireless communications systems require better performance, lower cost, and compact RF front-end footprint. The RF front-end module development and its level of integration are, thus, continuous challenges. In most of the presently used microwave integrated circuit technologies, it is difficult to integrate the passives efficiently with required quality. Another critical obstacle in the design of passive components, which occupy the highest percentage of integrated circuit and circuit board real estate, includes the effort to reduce the module size. These issues can be addressed with multilayer substrate technology. A multilayer organic (MLO)-based process offers the potential as the next generation technology of choice for electronic packaging. It uses a cost effective process, while offering design flexibility and optimized integration due to its multilayer topology. We present the design, model, and measurement data of RF-microwave multilayer transitions and integrated passives implemented in a MLO system on package (SOP) technology. Compact, high Q inductors, and embedded filter designs for wireless module applications are demonstrated for the first time in this technology.     

Loss reduction in a coplanar waveguide on a planar lightwavecircuit (PLC) platform by quenching

The hybrid integration of semiconductor optoelectronic devices on a silica-based optical circuit is one of the key technologies by which to realize opto-electronic components for high-speed wavelength division multiplexing (WDM). However, a coplanar waveguide (CPW) on a silicon-terraced silica (STS)-type planar lightwave circuit (PLC)-platform has a large propagation loss compared with one on a conventional ceramic substrate. We discuss the reduction of the propagation loss of a CPW on a PLC-platform. First we prove that this CPW loss originates from an increase of the loss tangent (tan δ) induced by the thermal donors (TD's) which connect with oxygen in the silicon substrate during the silica deposition process. Second we introduce quenching to eliminate the TD's, and drastically reduce the loss of a CPW on a 30 μm-thick silica from 2.7 to 0.6 dB/cm at 10 GHz. This loss value is almost the same as that of a CPW on a ceramic substrate. Moreover we fabricated a LD module using a 50 mm-long improved CPW on a PLC-platform. The small signal frequency response characteristics of this module reveal that the improved CPW can be applied as a cm-order electrical circuit in a 10 Gb/s module. This exhibits that an established electronic circuit technology including a multi-chip module (MCM) for a microwave application can be developed on a PLC-platform     

Single mode fiber MT-RJ SFF transceiver module using opticalsubassembly with a new shielded silicon optical bench

Demand for a compact cost reduced optical transceiver has arisen. Small form factor (SFF) optical transceivers are expected to meet this demand. A new concept optical module based on V-grooved silicon optical bench (SiOB) technology, that enables a passive alignment of optical fibers and optical devices is expected to reduce the cost. MT-RJ SFF optical transceivers require this new packaging technique because the distance between input and output optical axes is shorter than conventional transceivers. However, crosstalk between a transmitter and a receiver is a big issue to be solved because the distance between optical axes of the laser diode (LD) and the photo diode (PD) is only 0.75 mm. It is difficult to reduce the crosstalk in a SiOB because large electromagnetic coupling exists due to the conductivity of a silicon substrate. A newly developed, low crosstalk optical subassembly (OSA) with a single mode fiber MT-RJ receptacle and the SFF transceiver module are reported. We have analyzed a mechanism of electrical crosstalk in a SiOB and developed a shield structure to reduce it. The crosstalk in the OSA with shielded SiOB was reduced over 20 dB compared to the unshielded SiOB     

An embedded overlay concept for microsystems packaging

An embedded overlay concept for packaging hybrid components containing microelectromechanical systems (MEMS) is described. This packaging process is a derivative of the chip-on-flex (COF) process currently used for microelectronics packaging. COF is a high performance, multichip packaging technology in which die are encased in a molded plastic substrate and interconnects are made via a thin-film structure formed over the components. A laser ablation process has been developed which enables selected areas of the COF overlay to be efficiently ablated with minimal impact to the packaged MEMS devices. Analysis and characterization of the ablation procedures used in the standard COF process was performed to design a new procedure which minimized the potential for heat damage to exposed MEMS devices. The COF/MEMS packaging technology is well-suited for many microsystem packaging applications such as micro-optics and radio frequency (RF) devices.     

埋置型叠层微系统封装技术

包含微机电系统(MEMS)混合元器件的埋置型叠层封装,此封装工艺为目前用于微电子封装的挠曲基板上芯片(COF)工艺的衍生物.COF是一种高性能、多芯片封装工艺技术,在此封装中把芯片包入模塑塑料基板中,通过在元器件上形成的薄膜结构构成互连.研究的激光融除工艺能够使所选择的COF叠层区域有效融除,而对封装的MEMS器件影响...