Efficient Path Delay Test Generation for Custom Designs

Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.     

Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing

In this study, a novel path clustering technique for adaptive path delay testing, where the test paths are altered according to the extracted device parameters, is proposed. The proposed algorithm is based on the k-means++ algorithm. By considering the probability function of the die-to-die systematic process variation, the proposed algorithm clusters path sets to minimize the total number of test paths. A figure of merit for clustering, which represents the expected number of test paths, is also proposed for quantitatively evaluating path clustering under different conditions. The proposed clustering method is evaluated numerically by applying it to the OpenCores benchmark circuit. Using our clustering technique, the average number of test paths in the adaptive test is reduced to less than 92 % compared with those in the conventional test. In addition, adaptive testing using the proposed technique can reduce the test patterns by 94.26 % while retaining the test quality.     

基于电子束探测技术的VLSI路径延时故障测试方法

介绍了将电子束探测（ＥＢ－Ｐ）技术应用于路径延时故障的测试。首先用ＥＢ－Ｐ的工作原理和实验结果说明了用ＥＢ－Ｐ测量路径延时的可行性;随后讨论了一种将ＥＢ－Ｐ用作测试点的测试点插入技术。     

Functional Constraints vs. Test Compression in Scan-Based Delay Testing

We present an approach to prevent overtesting in scan-based delay test. The test data is transformed with respect to functional constraints while simultaneously keeping as many positions as possible unspecified in order to facilitate test compression. The method is independent of the employed delay fault model, ATPG algorithm and test compression technique, and it is easy to integrate into an existing flow. Experimental results emphasize the severity of overtesting in scan-based delay test. Influence of different functional constraints on the amount of the required test data and the compression efficiency is investigated. To the best of our knowledge, this is the first systematic study on the relationship between overtesting prevention and test compression.     

嵌入式系统数据共享存储器的实现

有的嵌入式系统中需要使用共享存储器进行数据交换,常用的共享存储器有DPRAM(双口内存)、PRAM(多口内存)、FIFO等.传统的DPRAM虽然简单易用,但是容量小,成本高.文中提出一种使用SRAM和PLD(可编程逻辑器件)实现共享存储的方法,应用于嵌入式系统的大容量高速数据交换,并给出一个实例.简单介绍了传统DPRAM的特点及使用方法,以及实现模拟DPRAM的方法和验证办法,比较了这种模拟DPRAM与传统DPRAM的优缺点,给出了改进的方案.     

Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects

We propose a new path delay fault model called the transition path delay fault model. This model addresses the following issue. The path delay fault model captures small extra delays, such that each one by itself will not cause the circuit to fail, but their cumulative effect along a path from inputs to outputs can result in faulty behavior. However, non-robust tests for path delay faults may not detect situations where the cumulative effect of small extra delays is sufficient to cause faulty behavior after any number of extra delays are accumulated along a subpath. Under the new path delay fault model, a path delay fault is detected when all the single transition faults along the path are detected by the same test. This ensures that if the accumulation of small extra delays along a subpath is sufficient to cause faulty behavior, the faulty behavior will be detected due to the detection of a transition fault at the end of the subpath. We discuss the new model and present experimental results to demonstrate its viability as an alternative to the standard path delay fault model. We describe an efficient fault simulation procedure for this model. We also describe test generation procedures. An efficient test generation procedure we discuss combines tests for transition faults along the target paths in order to obtain tests that satisfy the requirements of the new model.     

一种用于嵌入式闪存的低压灵敏放大器(英文)

提出了一种适合于低电压嵌入式闪存的灵敏放大器。该灵敏放大器采用了增强电流感应的方法,使得电源电压可以降到1.5V及其以下。灵敏放大器中采用的动态位线箝位电路可以提高位线预充速度并减小功耗。本电路在0.13μm的Flash工艺中实现。测试结果表明:提出的灵敏放大器在电源电压为1.5V时,访问时间是25ns;在电源电压为1.2V时,访问时间是32ns。     

Efficient BISR Techniques for Embedded Memories Considering Cluster Faults

Instead of the traditional spare row/column redundancy architectures, block-based redundancy architectures are proposed in this paper. The redundant rows/columns are divided into row/column blocks. Therefore, the repair of faulty memory cells can be performed at the row/column-block level. Moreover, the redundant row/column blocks can be used to replace faulty cells anywhere in the memory array. This global characteristic is helpful for repairing cluster faults. The proposed redundancy architecture can be easily integrated with the embedded memory cores. Based on the proposed global redundancy architecture, a heuristic modified essential spare pivoting (MESP) algorithm suitable for built-in implementation is also proposed. According to experimental results, the area overhead for implementing the MESP algorithm is very low. Due to efficient usage of redundancy, the manufacturing yield, repair rate, and reliability can be improved significantly.      

Testing and Diagnosis Methodologies for Embedded Content Addressable Memories

Embedded content addressable memories (CAMs) are important components in many system chips where most CAMs are customized and have wide words. This poses challenges on testing and diagnosis. In this paper two efficient March-like test algorithms are proposed first. In addition to typical RAM faults, they also cover CAM-specific comparison faults. The first algorithm requires 9N Read/Write operations and 2(N + W) Compare operations to cover comparison and RAM faults (but does not fully cover the intra-word coupling faults), for an N × W-bit CAM. The second algorithm uses 3N log₂ W Write and 2W log₂ W Compare operations to cover the remaining intra-word coupling faults. Compared with the previous algorithms, the proposed algorithms have higher fault coverage and lower time complexity. Moreover, it can test the CAM even when its comparison result is observed only by the Hit output or the priority encoder output. We also present the algorithms that can locate the cells with comparison faults. Finally, a CAM BIST design is briefly described.     

单向双端口SRAM的测试算法

描述了一种检测单向双端口 SRAM失效的算法 ,采用了基于字的测试方法 ,可以有效地检测字间失效、字内失效和同时读写失效 ,具有失效覆盖率高和测试时间复杂度低的优点。     

Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test

A system-on-chip (SOC) usually consists of many memory cores with different sizes and functionality, and they typically represent a significant portion of the SOC and therefore dominate its yield. Diagnostics for yield enhancement of the memory cores thus is a very important issue. In this paper we present two data compression techniques that can be used to speed up the transmission of diagnostic data from the embedded RAM built-in self-test (BIST) circuit that has diagnostic support to the external tester. The proposed syndrome-accumulation approach compresses the faulty-cell address and March syndrome to about 28% of the original size on average under the March-17N diagnostic test algorithm. The key component of the compressor is a novel syndrome-accumulation circuit, which can be realized by a content-addressable memory. Experimental results show that the area overhead is about 0.9% for a 1Mb SRAM with 164 faults. A tree-based compression technique for word-oriented memories is also presented. By using a simplified Huffman coding scheme and partitioning each 256-bit Hamming syndrome into fixed-size symbols, the average compression ratio (size of original data to that of compressed data) is about 10, assuming 16-bit symbols. Also, the additional hardware to implement the tree-based compressor is very small. The proposed compression techniques effectively reduce the memory diagnosis time as well as the tester storage requirement.     

Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories

Error correction code (ECC) and built-in self-repair (BISR) techniques have been widely used for improving the yield and reliability of embedded memories. The targets of these two schemes are transient faults and hard faults, respectively. Recently, ECC is also considered as a promising solution for correcting hard error to further enhance the fabrication yield of memories. However, if the number of faulty bits within a codeword is greater than the protection capability of the adopted ECC scheme, the protection will become void. In order to cure this drawback, efficient logical to physical address remapping techniques are proposed in this paper. The goal is to reconstruct the constituent cells of codewords such that faulty cells can be evenly distributed into different codewords. A heuristic algorithm suitable for built-in implementation is presented for address remapping analysis. The corresponding built-in remapping analysis circuit is then derived. It can be easily integrated into the conventional built-in self-repair (BISR) module. A simulator is developed to evaluate the hardware overhead and repair rate. According to experimental results, the repair rate can be improved significantly with negligible hardware overhead.     

On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation

A new framework for generating test sets with high test efficiency for path delay faults (PDFs) is presented. The proposed method is based on a data structure that can implicitly represent all sensitizable PDFs in a circuit, along with all their corresponding tests. A path and test implicit method to construct such a data structure, for various path sensitization types, is presented. It uses zero-suppressed binary decision diagram (ZBDD) representations of irredundant sum-of-products (ISOPs), and requires only a polynomial number of standard ZBDD operations. Consequently, an ATPG algorithm that can exploit the properties of the proposed structure to derive tests with maximal test efficiency is presented. The obtained experimental results on the ISCAS’85 and enhanced full-scanned version of the ISCAS’89 benchmarks demonstrate that the proposed framework is scalable in terms of test efficiency and can generate compact test sets for critical PDFs.     

Hierarchical Delay Test Generation

Delay testing is used to detect timing errors in a digital circuit.In this paper, we report a tool called MODET forautomatic test generation for path delay faults in modular combinational circuits. Our technique usesprecomputed robust delay tests for individual modules to computerobust delay tests for the module-level circuit. We present alongest path theorem at the module level ofabstraction which specifies the requirements for path selectionduring delay testing. Based on this theorem, we propose a pathselection procedure in module-level circuits and report efficientalgorithms for delay test generation. MODET hasbeen tested against a number of hierarchical circuits with impressivespeedups in relation to gate-level test generation.     

Efficient Path Selection for Delay Testing Based on Path Clustering

In this paper, we introduce a way of modeling the differences between the calculated delays and the real delays, and propose an efficient path selection method for path delay testing based on the model. Path selection is done by judging which of two paths has the larger real delay by taking into account the ambiguity of calculated delay, caused by imprecise delay modeling as well as process disturbances. In order to make precise judgment under this ambiguity, the delays of only the unshared segments of the two paths are evaluated. This is because the shared segments are presumed to have the same real delays on both paths.The experiments used the delays of gates and interconnects, which were calculated from the layout data of ISCAS85 benchmark circuits using a real cell library. Experimental results show the method selects only about one percent of the paths selected by the most popular method.     

Power and Substrate Noise Tolerance of Configurable Embedded Memories in SoC

When subject to various power and substrate noise, configurable embedded memories in multimedia SoCs are importantly affected with pattern-dependant soft failures. This work investigates the effects of such failures on memory cells, arrays and circuit design. The ground bounce reduces the memory cell current more than the supply voltage drop or the substrate bias dip. A noise track-and-filter (NTAF) architecture, which is a self-timed architecture with specific layout patterns, is presented to provide the required timing relaxation, while minimizing the speed degradation. This NTAF method provides greater noise tolerance and design for manufacturing (DFM) capability. Configurable embedded SRAM and ROM in 0.18 μ m CMOS process are studied.Meng-Fan Chang received the B.S. degree in electrical engineering from National Cheng-Kung University in 1991. He received the M.S. degree in electrical engineering from The Pennsylvanian State University, University Park, PA, in 1996. He is currently working toward the Ph.D. degree at the Institute of Electronic Engineering, National Chiao Tung University, Hsin-Chu, Taiwan.During 1991–1993, he joined Army of Taiwan as second lieutenant in electronic communication. From 1993 to 1994, he designed motherboards in ABIT Computer Corp., Taipei, Taiwan. During 1996–1997, he designed SRAM/ROM compilers in Mentor Graphics Corp., Warren, New Jersey. From 1997 to 2001, he designed SRAM and managed the IP Validation Program in Design Service Division (DSD) of TSMC, Hsin-Chu, Taiwan. Since 2001, he jointed Intellectual Property Library Company (IPLib), Hsin-Chu, Taiwan. He is in charge of Silicon-IP Division. He is engaged in the research and development of embedded Flash, SRAM/ROM compilers, flat-cell mask ROM and mixed-signal IPs.His research interest included embedded memories, low-power circuit, integration issues of silicon-IP in SoC, CMOS RF and LTCC RF circuit.Kuei Ann Wen was born in Keelung, Taiwan, R.O. China in 1961. She received the B.E.E., M.E.E. and Ph.D. degrees from the Dept. of Electrical and Computer Enginerring a National Cheng-Kung University, Taiwan, R.O. China in 1983, 1985 and 1988, respectively. She is currently a professor in the Dept. of EE at national Chiao-Tung University, Taiwan, R.O. China. At the present time, she is also involved in several research projects from Wireless Communication Consortium () and Academic Center of Excellence (), which is under supervision of Dept. of Higher Education, Council of Academic Reviewer & Evaluation of R.O. China. Dr. Kuei-Ann Wen’s interests are in the areas of wireless communication system, RF circuit design, video signal processing & transmission.     

嵌入式存储器MBIST设计中内建自诊断功能研究

针对大规模嵌入式存储器可测性设计技术——存储器内建自测试（MBIST）中的故障诊断问题,介绍了MBIST设计的扩展功能——存储器内建自诊断（MBISD）。在引入存储器内建自测试的基础上,详细分析了存储器内建自诊断模块根据输出故障信息自动分析器件失效原因、并对失效单元进行故障定位和识别的基本原理及其中的关键算法,并用一块SRAM的MBIST设计（采用Mentor公司的MBISTArchitect完成）中的MBISD具体实例进行了仿真验证。存储器内建自诊断的应用,大大提高了存储器的成品率。     

Efficient Path Delay Testing Using Scan Justification

Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip‐flop and test algorithm to overcome some of the problems in delay testing. In the proposed test algorithm, the second test pattern is generated by scan justification, and the first test pattern is processed by functional justification. In the conventional functional justification, it is hard to generate the proper second test pattern because it uses a combinational circuit for the pattern. The proposed scan justification has the advantage of easily generating the second test pattern by direct justification from the scan. To implement our scheme, we devised a new scan in which the slave latch is bypassed by an additional latch to allow the slave to hold its state while a new pattern is scanned in. Experimental results on ISCAS’89 benchmark circuits show that the number of testable paths can be increased by about 45% over the conventional functional justification.     

Robust Coupling Delay Test Sets

One of the most challenging problems in high-level testing is to reduce the size of a high-level test set while ensuring an adequate fault coverage for various implementations of a function under test. A small and high-coverage test set called a robust coupling delay test set (RCDTS) is derived from the coupling delay test set proposed previously. A partial ordering relationship among delay tests in certain implementations called ??restricted?? gate networks is used to reduce the size of test sets. The RCDTS still detects all robust path delay faults. This result is extended further to the more general balanced inversion parity networks. A test generation program RTGEN for RCDTSs is then developed, and experiments with it show that significant test set reduction can be achieved.     

Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories

This paper proposes a code placement problem, its ILP formulation, and a heuristic algorithm for reducing the total energy consumption of embedded processor systems including a CPU core, on-chip and off-chip memories. Our approach exploits a non-cacheable memory region for an effective use of a cache memory and as a result, reduces the number of off-chip accesses. Our algorithm simultaneously finds a code layout for a cacheable region, a scratchpad region, and the other non-cacheable region of the address space so as to minimize the total energy consumption of the processor system. Experiments using a commercial embedded processor and an off-chip SDRAM demonstrate that our algorithm reduces the energy consumption of the processor system by 23% without any performance degradation compared to the best result achieved by the conventional approach.