Optical switch emulation in programmable software router testbed

A programmable optical router is a key enabler for dynamic service provisioning in Future Internet scenarios. It is equipped with optical switching hardware to forward information at hundreds of Gigabits/s rates and above, controlled and managed through modular and flexible procedures according to emerging standards. The possibility to test such costly optical architectures in terms of logical and physical performance, without implementing complex and expensive testbeds, is crucial to speed-up the development process of high-performance routers. To this purpose, this paper introduces the software-based emulation testbed of a programmable optical router, which is here developed and applied to test optical switching fabrics. Accurate characterization of the optical devices and physical layer aspects is implemented with the Click software router environment. Power loss and optical signal-to-noise-ratio evaluation are provided through accurate software representation of the physical characteristics of the optical devices employed. The scalability of the proposed emulation testbed is also assessed on standard PC hardware. All the obtained results prove the effectiveness of the proposed tool to emulate an optical router at different levels of granularity.     

A current memory cell with switch feedthrough reduction by errorfeedback

A new switch feedthrough suppressing current memory cell, capable of accurately memorizing low current levels is presented. The scheme operates by feeding back a fraction of the error current to the storage node whose voltage is adjusted so that the error is reduced to zero. Using the feedback compensation scheme, absolute current error of less than 0.1% was achieved even at ultra-low current levels of 10 nA. The negative feedback circuit consumes negligibly low power and can be laid in a very small area. With this scheme, memory accuracy is traded for error correction speed, a feature common to all feedback-based switch feedthrough reduction schemes. The feedback compensated current memory cell can be used for low-power high-background infrared focal-plane readout electronics featuring in-pixel background suppression     

Reconfigurable ATM switch fabrics using traffic history

An ATM switch fabric which is capable of being reconfigured based on the statistics of a previous time period, is introduced. Taking under consideration the strong correlation between ports in a campus or LAN ATM switch, the proposed architecture exhibits improved performance. We prove the performance improvement, by applying data collected from a campus production ATM switch onto our proposed architecture     

GaP electroluminescent memory switch

M.I.S. structures in which the semiconductor is GaP and the insulator a native oxide of GaP exhibit switchtng and non volatile memory properties as well as electroluminescence that is green under forward bias and orange under reverse bias. The switching and memory properties are thought to be due to a forming process in the oxide layer.     

On fixed-database universal data compression with limited memory

The amount of fixed side information required for lossless data compression is discussed. Nonasymptotic coding and converse theorems are derived for data-compression algorithms with fixed statistical side information (“training sequence”) that is not large enough so as to yield the ultimate compression, namely, the entropy of the source     

On sliding-window universal data compression with limited memory

Nonasymptotic coding and converse theorems are derived for universal data compression algorithms in cases where the training sequence (“history”) that is available to the encoder consists of the most recent segment of the input data string that has been processed, but is not large enough so as to yield the ultimate compression, namely, the entropy of the source     

Optical switching: switch fabrics, techniques, and architectures

The switching speeds of electronics cannot keep up with the transmission capacity offered by optics. All-optical switch fabrics play a central role in the effort to migrate the switching functions to the optical layer. Optical packet switching provides an almost arbitrary fine granularity but faces significant challenges in the processing and buffering of bits at high speeds. Generalized multiprotocol label switching seeks to eliminate the asynchronous transfer mode and synchronous optical network layers, thus implementing Internet protocol over wavelength-division multiplexing. Optical burst switching attempts to minimize the need for processing and buffering by aggregating flows of data packets into bursts. In this paper, we present an extensive overview of the current technologies and techniques concerning optical switching.     

Performance comparison of switch architectures with shareable parallel memory modules

The class of switches with shareable parallel memory modules include those switches that use parallel memory modules which are physically separate but logically shared. The two main classes of such architectures namely the Shared Multibuffer (SMB) based switch and the Sliding-Window (SW) based packet switch both deploy shareable parallel memory modules, however they differ in the switching scheme used by them to store incoming packets and transfer packets among different switch ports. In this letter, we investigate and compare the performance of switching schemes deployed by these two classes of switching architectures. We compare throughput and packet loss performance of these two switches under conditions of identical traffic type, switch configuration and memory resource deployed.     

一种端口速率可变的共享存储器交换

针对局域网和城域网中的多种数据传输速率结构,该文提出了一种共享存储器交换结构,在普通共享存储器交换结构的基础上,对支持可变的端口速率,以及支持变长数据包交换进行了改进,所提出的交换结构还具有自同步特点,即各输入输出端口之间不需要全局同步;同时还考虑了对变长数据包的队列管理。     

DISA: a robust scheduling algorithm for scalable crosspoint-based switch fabrics

This paper presents and analyzes a high-performance, robust, and scalable scheduling algorithm for input-queued switches called distributed sequential allocation (DISA). In contrast to pointer-based arbitration schemes, the proposed algorithm is based on a synchronized output reservation process, whereby each input selects a designated output while taking into consideration both local transmission requests and the availability of global resources. The distinctiveness of the algorithm lies in its ability to offer high performance when multiple cells are transmitted within each switching interval. Relaxed switching-time requirements allow for the incorporation of commercially available crosspoint switches. The result is a pragmatic and scalable solution for high port-density switching platforms. The efficiency of the scheme and its robustness in the presence of admissible traffic, without the need for speedup, is established through analysis and computer simulations. Performance results are shown for various traffic scenarios including nonuniform destination distribution, correlated arrivals and multiple classes of service.     

Static memory element based on electron Y-branch switch

A compact memory element, based on an electron Y-branch switch, has been realised. Memory operation is a result of bilateral feedback coupling of each of the branches to the opposing side-gate. D-flip-flop in addition to RS-flip-flop operation is demonstrated.     

An electron beam activated switch and associated memory

A new type of electron beam activated switch (EBAS) is described which utilizes electron beam induced charge storage in the metal-oxide-semiconductor (MOS) system. The state of the EBAS is determined by monitoring the surface conductance of the semiconductor. After discussing the basic charge-storage phenomena, memory arrays that use the electron beam for storing and reading information are described. A matrix array of EBASs in which information is stored using the electron beam and read by row-column access circuits is discussed in detail. The time to store a bit of information is a function of the current density of the electron beam; an approximate dosage of 10^-5C/cm²is required for storage. A memory design using Schlesinger's microspot tube for the electron optics is discussed. It is shown that storage of 1.0 × 10⁷bits per tube should be possible with presently available electron optical design and semiconductor technology.     

Fabrication process not limited by the lithography resolution of lateral phase change memory

To improve the performance of phase change memory (PCM) and reduce the cost of fabrication, we propose a new lateral PCM structure based on the technology of angle evaporation to define the critical dimension controllable, not limited by the limitation of lithography resolution. The fabrication process is cost-effective. PCM cells featured 80 nm×100 nm were successfully demonstrated, although the resolution of the aligned used was 1 µm only. Compared with the traditional lateral PCM structure, finite element simulation results show that the new structure has better thermal stability.     

The sliding-window packet switch: a new class of packet switch architecture with plural memory modules and decentralized control

Shared-memory based packet switches are known to provide the best possible throughput performance for bursty data traffic in high-speed packet networks and internets compared with other buffering strategies under conditions of identical memory resources deployed in the switch. However, scaling of shared-memory packet switches to a larger size has been restricted mainly due to the physical limitations imposed by the memory-access speed and the centralized control for switching functions in shared-memory switches. A new scalable architecture for a shared-memory packet switch, called the sliding-window (SW) switch, is proposed to overcome these limitations. The SW switch introduces a new class of switching architecture, where physically separate multiple memory modules are logically shared among all the ports of the switch, and the control is decentralized. The SW switch alleviates the bottleneck caused by the centralized control of switching functions in large shared-memory switches. Decentralized switching functions enable the SW switch to operate in a pipeline fashion to enhance scalability and switching capacity compared with that of previously known classes of shared-memory switch architecture.     

Hard-disk based development systems with multiprocessor emulation

An entirely new series of hard-disk based development systems is introduced, with particular reference to multiply in-circuit emulation stations for multi-user or multiprocessing configurations.     

Recursive limited memory filtering and scattering theory (Corresp.)

Redheffer scattering theory is reviewed in a generalized setting as a method to derive recursive solutions of linear two-point boundary value problems (TPBVP) over arbitrarily varying intervals. The results can be used to derive a complete solution for the problem of limited-memory (or sliding-window) estimation, when a usual state-space model for the signal is available. Recursive limited-memory filters are derived for both continuous and discrete time signals.     

基于有限存储的简约空间序列二次规划算法研究

为了求解过程系统中自由度相对较大一些的大规模优化命题,对简约空间序列二次规划（reduced successive quadratic programming,RSQP）算法进行了改进和扩展,提出了基于有限存储的简约空间序列二次规划算法.该算法通过有限存储技术隐式的表示RSQP算法中的两个最大矩阵,大大减少了优化计算过程中的存储需求,并对有限存储技术应用到RSQP算法中后Hessian阵的更新和基变量的选择进行了特殊处理。该算法的求解性能通过benchmark算例进行了测试,并被应用到两个过程系统优化实例。计算结果表明,采用该方法求解自由度相对较大的问题可以大大减少内存消耗,从而可大大提高算法的优化求解效率。     

A large ATM switch based on memory switches and optical starcouplers

The authors propose a large asynchronous transfer mode (ATM) switch architecture based on memory switches of the type being developed by several research groups and on optical star couplers. Fast contention resolution makes it possible to combine a number of these modules, memory switches, and optical stars in order to attain a capacity of 2.5 Tb/s. This switch architecture has a relatively small failure group size of 128 STS-3 lines out of a total of 16384. The scaling of the switch to smaller capacities is discussed, showing how tradeoffs in the various parameters can be used to overcome particular technological limitations. Fault tolerance and recovery schemes are presented, showing that with minimal increase to the switch complexity and cost, a very reasonable fault recovery scheme is available for almost every sort of failure     

Three dimensional finite-difference time-domain slotline analysison a limited memory personal computer

In order to reduce computer memory and computational time required by three dimensional Finite-Difference Time-Domain (FDTD) microwave passive component analysis, two strategies are developed in this paper. First, the recently reported dispersive boundary condition (DEC) is modified thereby enabling the absorbing boundary to be located near to the main field area; second, an exact source plane field distribution itself produced by the FDTD algorithm is adopted to improve numerical accuracy. This leads to a reduction in computer memory requirements. As an example, a full-wave 3D FDTD analysis of a slotline is performed on a 33 MHz PC486. The dispersion characteristic of the slotline is presented up to 1000 GHz this agrees well with that of closed form formula. When compared with previous slotline solutions, frequency range results are extended by an octave and less than 9 percent of the computer memory previously required is demanded. The unique and highly efficient combination of the two strategies presented here could be applied to other microwave waveguide component analyses     

控制最大误差的无线多跳网络场景仿真算法

如何用固定实验床仿真任意无线多跳网络场景是移动自组织网络仿真的基本问题,但现有的基于射频信号能量控制的无线网络仿真实例中还没有对这个问题进行深入讨论.对基于射频信号能量控制的无线多跳网络场景仿真问题进行数学建模,并以控制最大仿真误差为求解思路,提出一种仿真算法--匹配有解条件法.模拟实验表明,该算法能够求解无线多跳网络场景仿真问题,并给出最大误差.