ASIC设计中时钟偏移分析

目前的ASIC设计中,时钟偏移对同步数字电路的影响越来越大,它也越来越受到高速电路设计者的关注,因此如何解决它给电路带来的不利影响成了设计中的重要挑战、文章分析了时钟偏移的产生机理,然后提出了怎样使用CTS在时钟树中插入不同驱动能力的缓冲器,以平衡时钟网络,最后还分析了如何利用有用的时钟偏移来改善电路的时序。     

ASIC设计中时钟偏移分析

目前的ASIC设计中,时钟偏移对同步数字电路的影响越来越大,它也越来越受到高速电路设计者的关注,因此如何解决它给电路带来的不利影响成了设计中的重要挑战.分析了时钟偏移的产生机理,提出了怎样使用CTS在时钟树中插入不同驱动能力的缓冲器,以平衡时钟网络,以及如何利用有用的时钟偏移来改善电路的时序.     

ASIC后端设计中的时钟偏移以及时钟树综合

目前的ASIC设计中,时钟偏移成为限制系统时钟频率的主要因素,时钟树综合技术通过在时钟网络中插入缓冲器来减小时钟偏移.但是,有时这样做并不能达到系统要求的时钟偏移.以一款SMIC 0.18μm工艺的DVBT数字电视解调芯片为例,分析了时钟偏移的产生原因.介殚绍了使用Synopsys公司Astro工具进行时钟树综合的方法,重点分析了在时钟树综合之前如何设置约束手动优化电路从而改善设计的时序,最后的流片结果证明该方法是有效的.     

同步电路设计中CLOCK SKEW 的分析

Clock skew是数字集成电路设计中一个重要的因素。本文比较了在同步电路设计中0clock skew和非0clock skew时钟分布对电路性能的影响，分析了通过调整时钟树中CLOCK SKEW来改善电路性能的方法，从而说明非0clock skew时钟分布是如何提高同步电路运行的最大时钟频率的。     

时钟树综合中的有效时钟偏移

为了解决用传统时钟树综合策略来设计芯片只能尽量减小时钟偏移,而不能满足时序收敛的问题,文中引入了有效时钟偏移的概念,并通过在TSMC0.13μm工艺下流片成功的芯片BES7000作为设计实例,分析了有效时钟偏移引入之后对改进时序建立时间的效果。     

时钟网格与时钟树设计方法对比研究

基于片上偏差对芯片性能的影响,分析对比了时钟树设计与时钟网格设计,重点分析了时钟网格抗OCV影响的优点,并利用实际电路应用两种方法分别进行设计对比,通过结果分析,验证了理论分析的正确性,证明在抗OCV及时序优化时钟网格方法具有很大的优势。     

多时钟源分割方法在时钟树综合中的应用

本文以sha256算法模块的数字后端物理设计为例,提出了将多时钟源分割技术应用在传统时钟树综合中的方法。应用该方法后,利用有效时钟偏移,仅通过少量时钟缓冲器的插入就解决了该模块设计中的建立时间违例问题,大大降低了后续时序收敛工作的复杂度,将时序修复耗时缩短为采用传统方法的20%。     

合理偏差驱动的时钟线网构造及优化

提出了一种新的时钟布线算法,它综合了top-down和bottom-up两种时钟树拓扑产生方法,以最小时钟延时和总线长为目标,并把合理偏差应用到时钟树的构造中.电路测试结果证明,与零偏差算法比较,该算法有效地减小了时钟树的总体线长,并且优化了时钟树的性能.     

合理偏差驱动的时钟线网构造及优化

提出了一种新的时钟布线算法 ,它综合了 top- down和 bottom- up两种时钟树拓扑产生方法 ,以最小时钟延时和总线长为目标 ,并把合理偏差应用到时钟树的构造中 .电路测试结果证明 ,与零偏差算法比较 ,该算法有效地减小了时钟树的总体线长 ,并且优化了时钟树的性能     

一种宽频的数据时钟自恢复电路的设计

介绍了一种加宽数据时钟自恢复电路的可恢复时钟频率带宽的方法，重点提出了时钟锁定的检测电路及时钟输出的选择电路的设计，并进行了分析。     

一种有效的变线宽时钟布线算法

针对时钟布线提出了一种有效的变线宽算法。该算法通过对时钟树中各树枝延迟敏感度的分析,选择总体最优的连线进行变线宽处理,使得时钟树的路径延迟最小化。在延迟优化后,为了使时钟偏差小于给定的约束,通过变线宽对各种钟汇点的延迟进行全面的再分配,使延迟最大的时钟汇点延迟最小化,而延迟较小的路径延迟适当增加,以进一步改善时钟树延迟。实验结果表明,该算法有较高的运行效率,时钟树的路径路径和时钟偏差得到了显著的改     

Clock synchronization in wireless sensor networks using least common multiple

In this research, we propose the Clock Synchronization by Least Common Multiple (CSLCM) method to remove the clock offset and clock skew among the sensor nodes. The proposed CSLCM enables the nodes to reach a network synchronization time by calculating the least common multiple of their Clock Time Period (CTP). The network is organized into clusters and every node reaches the network synchronization time using its own CTP. Simulation results show that, the CSLCM algorithm is more efficient compared to the Average Time Synchronization with Pairwise messages (ATSP) in terms of accuracy, communication overhead, and computation overhead.     

数字电视发端调制器芯片时序优化设计与实现

设计数字集成电路时,关键是要满足时序的约束。时钟树综合是芯片设计后端优化时序过程中至关重要的一环,尤其是在复杂的超大规模高速集成电路设计中,它将直接影响最后的流片。其中时钟偏斜是影响时钟的重要因素。本文以SMIC 0.18μm工艺数字电视发端调制器芯片为例,前端提出新的获得同步分频时钟的方法,后端使用Synopsys的Astro工具来进行手动时钟树综合和时序优化,在满足时序设计要求的同时减小了芯片面积。     

Timing–driven variation–aware synthesis of hybrid mesh/tree clock distribution networks

Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as meshes and crosslinks, are employed to reduce skew and also to mitigate skew variations. These networks, however, increase the dissipated power while consuming significant metal resources. Several methods have been proposed to trade off power and wires to reduce skew. In this paper, an efficient algorithm is presented to reduce clock skew variations while minimizing power dissipation and metal area overhead. With a combination of nonuniform meshes and unbuffered trees (UBT), a variation-tolerant hybrid clock distribution network is produced. Clock skew variations are selectively reduced based on circuit timing information generated by static timing analysis (STA). The skew variation reduction procedure is prioritized for critical timing paths, since these paths are more sensitive to skew variations. A framework for skew variation management is proposed. The algorithm has been implemented in a standard 65 nm cell library using standard EDA tools, and tested on several benchmark circuits. As compared to other nonuniform mesh construction methods that do not support managed skew tolerance, experimental results exhibit a 41% average reduction in metal area and a 43% average reduction in power dissipation. As compared to other methods that employ skew tolerance management techniques but do not use a hybrid clock topology, an 8% average reduction in metal area and a 9% average reduction in power dissipation are achieved.     

时钟畸变对多级移位寄存器的影响及其消除技术

本文分析了时钟畸变对移位寄存器的影响 ,提出了几种消除技术 ,并分析了它们的适用场合。     

SmipRef: An efficient method for multi-domain clock skew scheduling

Conventional clock skew scheduling (CSS) for sequential circuits can be solved effectively using methods including the parametric shortest path algorithm and Howard's algorithm. Nevertheless, its application is practically limited due to the difficulties in reliably implementing a large set of arbitrary dedicated clock delays for flip-flops. Thus multi-domain clock skew scheduling (MDCSS) was proposed to tackle this by constraining the total number of clock delays. However, this new problem is hard to solve optimally in general. In this paper, we propose a novel method to efficiently solve it. Under mild restrictions, the problem is transformed into a special mixed integer linear programming problem, which can be solved optimally using similar techniques for the CSS problem. Then the solution quality is further improved by a critical-cycle-oriented refinement. As a result, our method obtains optimal solutions for 88 of the 93 tests on ISCAS89 benchmarks. The experimental results on large circuits in Opencores benchmarks also demonstrate its efficiency of at least one order faster than existing algorithms. To improve the runtime performance, we also devise a graph pruning algorithm that can be applied to methods for the MDCSS problem as a preprocessing step. Its application on our method shows a speedup of 2.66X on average.     

一种改进型FBT时钟树结构

针对混合型鱼骨平衡树(FBT)时钟结构的优缺点,结合宏单元的特性,提出了一种针对触发器与宏单元共存的改进型FBT时钟树结构,并总结出一种快速实现该时钟树的方法。在相同条件下,采用该方法实现的时钟树结构与二叉树型、鱼骨型时钟结构和传统的FBT时钟树结构进行比较,结果显示:鱼骨型时钟结构的时序质量最差;改进型FBT时钟树比二叉树型时钟树减少了15%的时钟延时和35%的时钟偏差,且整个过程的实现时间是传统FBT时钟树的30%。     

一种非零偏差时钟网布线算法

特定的非零偏差时钟网比零偏差时钟网更具优势,它有助于提高时钟频率、降低偏差的敏感度.文章提出了一种新的非零偏差时钟树布线算法,它结合时钟节点延时和时钟汇点位置,得到一个最大节点延时次序合并策略,使时钟树连线长度变小.实验结果显示,这种算法与典型的最邻近选择合并策略相比较,可以减少20%～30%的总连线长度.