Analysis of harmonic distortion in single-channel MOS integrated circuits

Presents a general analysis for the calculation of harmonic distortion in single-channel monolithic analog MOS integrated circuits. Power series expressions are obtained for basic stages often used in an analog MOS technology. These include the depletion load inverter, enhancement load inverter, depletion load source follower, enhancement load source follower, and the differential pair. From the power series expressions, the second-order harmonic distortion is calculated. These results are compared with data obtained from a test chip.     

Harmonic performance of single-channel MOS integrated circuits

Using simple square-law models for both the MOSFET current-voltage characteristics and the relationship between the threshold voltage and the source-to-substrate voltage, simple expressions are presented for predicting the performance of the basic MOSFET circuits used in analog MOS technology. Using these expressions, the low-frequency gain and the second and third harmonic distortion performance of the enhancement-load inverters, enhancement-load source follower, depletion-load inverter, and depletion-load source follower can be easily predicted by hand calculations. The results obtained by using these expressions are compared with previously published measurements and calculations.     

Planar integration of E/D-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment

A planar-fabrication technology for integrating enhancement/depletion (E/D)-mode AlGaN/GaN high-electron mobility transistors (HEMTs) has been developed. The technology relies heavily on CF/sub 4/ plasma treatment, which is used in two separate steps to achieve two objectives: 1) active device isolation and 2) threshold-voltage control for the enhancement-mode HEMT formation. Using the planar process, depletion- and enhancement-mode AlGaN/GaN HEMTs are integrated on the same chip, and a direct-coupled FET logic inverter is demonstrated. Compared with the devices fabricated by a standard mesa-etching technique, the HEMTs by a planar process have comparable dc and RF characteristics with no obvious difference in the device isolation. The device isolation by a plasma treatment remains the same after 400 /spl deg/C annealing, indicating a good thermal stability. At a supply voltage (V/sub DD/) of 3.3 V, the E/D-mode inverters show an output swing of 2.85 V, with the logic-low and logic-high noise margins at 0.34 and 1.47 V, respectively.     

Monolithically integrated enhancement/depletion-mode AIGaN/GaN HEMT D flip-flop using fluorine plasma treatment

Depletion-mode and enhancement-mode AlGaN/GaN HEMTs using fluorine plasma treatment were integrated on one wafer. Direct-coupled FET logic circuits, such as an E/D HEMT inverter, NAND gate and D flip-flop, were fabricated on an AlGaN/GaN heterostructure. The D flip-flop and NAND gate are demonstrated in a GaN system for the first time. The dual-gate AlGaN/GaN E-HEMT substitutes two single-gate E-HEMTs for simplifying the NAND gate and shrinking the area, integrating with a conventional AlGaN/GaN D-HEMT and demonstrating a NAND gate. E/D-mode D flip-flop was fabricated by integrating the inverters and the NAND gate on the AlGaN/GaN heterostructure. At a supply voltage of 2 V, the E/D inverter shows an output logic swing of 1.7 V, a logic-low noise margin of 0.49 V and a logic-high noise margin of 0.83 V. The NAND gate and D flip-flop showed correct logic function demonstrating promising potential for GaN-based digital ICs.     

High-speed high-precision min/max circuits in CMOS technology

New voltage-mode min/max circuits are introduced that have a simple architecture. Unlike conventional winner-take-all or source follower based schemes, the proposed circuits are characterised by reduced voltage swing at all internal nodes and by a very low output impedance, which enables them to provide high-speed and high-precision operation. Their complexity grows linearly with the number of inputs. The characterisation of a test chip prototype has provided experimental verification of these features     

F等离子体处理增强型及耗尽型AlGaN/GaN HEMT集成的D触发器

耗尽型和F等离子体处理增强型高电子迁移率晶体管（HEMT）被集成在同一圆片上。增强型/耗尽型 HEMT反向器、与非门以及D触发器等直接耦合场效应晶体管逻辑电路被制作在AlGaN/GaN异质结上。D触发器在GaN体系中首次被实现。在电源电压为2伏的条件下,增强型/耗尽型反向器显示输出逻辑摆幅为1.7伏,逻辑低噪声容限为0.49伏,逻辑高噪声容限为0.83伏。与非门和D触发器的功能正确,证实了GaN基数字电路的发展潜力。     

Realization of quaternary logic circuits by n-channel MOS devices

A method to implement quaternary circuits using NMOS devices is proposed. The authors have designed a simplified elementary form of inverter and have implemented a series of fundamental logic and memory circuits. These circuits comprise MOS transistors with three values of enhancement-mode threshold voltage and one depletion-mode threshold voltage. The features of these circuits are a small number of MOS transistors, a simple structure, and an exact transfer characteristic. Several fundamental circuits such as inverter, NAND, NOR, and delta literal have been fabricated by conventional NMOS technology. Comparisons between the measured and calculated results indicate a good agreement, taking into account some back-bias effect. The performance of the inverter, including speed, noise margin, and pattern area, is also discussed.     

Some system design considerations for a high switching frequency PWM inverter

A sinusoidal PWM inverter is required to faithfully reproduce the control waveforms at the output with minimum distortion. This paper presents some design considerations for such an inverter. The choice of switching frequency is the main criterion which affects the output voltage harmonic distortion at high switching frequencies. This paper shows that there exists an optimum switching frequency above which the output harmonic distortion becomes more visible. The dead time generator circuit for a low cost inverter and effect of driver circuits on the output waveform are discussed. Experimental results from laboratory models are presented.     

Heric逆变器驱动电路研究与设计

传统Heric逆变器各个桥臂采用相同的驱动电路,造成保护功能的重复,文章针对Heric逆变电路上下桥臂的导通状态,对逆变器上、下桥臂驱动电路的功能进行了划分,分别设计了上、下桥臂驱动电路,使其实现互补配合的保护功能,并针对驱动电路中光耦隔离芯片输出失真的问题,在光耦输入侧加入驱动增强电路。对驱动电路进行测试,实验结果表明该驱动电路可靠性较高,在占空比变化范围较宽时失真度小,逆变器输出波形较好。     

Current-Mode Logic in Organic Semiconductor Based on Source-Gated Transistors

Due to the low mobility and the abundance of trap states in organic field-effect transistors (OFETs), the operation of conventional logic circuits-based OFETs needs a large voltage swing, and suffers large switching noise and low speed. In this letter, current-mode logic (CML) circuits composed of organic source-gated transistors (OSGTs) are proposed for high-speed signaling based on existing material and process technologies. Mixed-mode simulations show that CML circuits using simple resistive loads can still be operated much faster than an ideal conventional inverter with perfect active loads and OFETs free of traps. With the same supply voltage and device parameters, CML circuits can work with a wide range of signal swings. The superior analog performance of OSGTs is also shown to fit well with the design requirements for CML circuits in terms of low power supply, high output impedance, and stability.      

An enhanced slew rate source follower

A unity-gain buffer capable of high slew rates in both the positive and negative directions is presented. By sensing the drain current of the common-drain device in an NMOS source follower, the extent of slewing is detected, and the tail current of the source follower is dynamically adjusted. A buffer incorporating this strategy was implemented in a 2 μm p-well process. This buffer has over 4 times the negative-going slew rate and twice the bandwidth of a source follower, while requiring only 13% more static power. Moreover, the output voltage swing range is as large as that of a source follower. With a 20 pF output load, the measured 3-dB bandwidth was 9 MHz. The signal-to-total-harmonic-distortion ratio with 2 V_p-p sinewave input at a frequency of 2 MHz was better than 50 dB     

Use of active loads with MSM photodetectors in digital GaAs MESFETphotoreceivers

Illuminated metal-semiconductor-metal (MSM) photodetectors display a current-voltage characteristic that saturates with increasing bias voltage and resembles the output characteristics of a field-effect transistor (FET). It is shown that operating an MSM photodetector with a GaAs FET active load can produce output voltage signal swings of over 80% of the power supply voltage from less than a 1 decade change in the MSM photocurrent, which may in turn be produced by only a 0.1 mW change in the input optical power. This swing allows the circuit to be used as an extremely compact optical input to high-speed digital gate circuits without the need for any intervening amplifiers. For fully monolithic prototype optical input circuits, less than -6 dBm of peak optical input power provided noise-free switching of a standard buffered FET logic (BFL) inverter from DC up to 25 MHz     

A 3.3-V, low-distortion ISDN line driver with a novel quiescentcurrent control circuit

A U-interface line driver for a single-chip ISDN (integrated services digital network) NT (network termination) in an advanced 3.3-V, 0.5-μm CMOS technology is presented. It features a THD (total harmonic distortion) better than -68 dB for an output swing of 5 V_pp on a 67-Ω load in a band up to 60 kHz. A novel quiescent current control circuit is implemented. The advantages of this new approach lie in the reduction of the variation of the quiescent current and the facilitation of the driver's circuits and compensation scheme     

A 1-V BiCMOS rail-to-rail amplifier with n-channel depletion modeinput stage

A BiCMOS rail-to-rail operational amplifier capable of operating from supply voltages as low as 1 V is presented. The folded cascode input stage uses an nMOS depletion mode differential pair to provide rail-to-rail common mode voltage range while typically requiring only 40 fA of input bias current. The bipolar transistor differential-to-single-ended conversion network employs a low-voltage base current cancellation technique which provides high input stage voltage gain from a l-V supply yet allows a 3-V/μs slew rate capability. The bipolar transistor output stage uses a low-voltage translinear loop which maintains a low impedance signal path to the output common emitter power devices. This circuit topology enables the amplifier to achieve a 4-MHz bandwidth with 60° of phase margin. The output voltage can swing to within 50 mV of each supply rail. An “on-demand” base current boost technique will be presented which can provide up to 50 mA of output drive capability from a 5-V supply, yet consumes only a few microamps when the output is in the quiescent state. A low voltage level shift technique will be described which uses an n-channel depletion mode source follower to provide isolation between the input and output stages     

A 1-V, 8-bit successive approximation ADC in standard CMOS process

A 1-V 8-bit 50-kS/s successive approximation analog-to-digital converter (ADC) implemented in a conventional 1.2-μm CMOS process is presented. Low voltage, large signal swing sample-and-hold, and digital-to-analog conversion are realized based on inverting op-amp configurations with biasing currents added to the op-amp negative input terminal so that the op-amp input common-mode voltages can be biased near ground to minimize the supply voltage. At the same time, the input and output quiescent voltages can be set at half of the supply rails. A low-voltage latched comparator is realized based on the current-mode approach. The entire ADC including all the digital circuits consumes less than 0.34 mW. An effective number of bits of 7.9 was obtained for a 1-kHz 850-mV peak-to-peak input signal     

An accurate approach of nonlinearity compensation for VSI inverter output voltage

An accurate nonlinearity compensation technique for voltage source inverter (VSI) inverters is presented in this paper. Because of the nonlinearity introduced by the dead time, turn-on/off delay, snubber circuit and voltage drop across power devices, the output voltage of VSI inverters is distorted seriously in the low output voltage region. This distortion influences the output torque of IM motors for constant V/f drives. The nonlinearity of the inverter also causes 5th and 7th harmonic distortion in the line current when the distributed energy system operates in the grid-connected mode, i.e., when the distributed energy system is parallel to a large power system through the VSI inverter. Therefore, the exact compensation of this nonlinearity in the VSI inverter over the entire range of output voltage is desirable. In this paper, the nonlinearity of VSI inverter output voltage and the harmonic distortion in the line current are analyzed based on an open-loop system and a L-R load. By minimizing the harmonic component of the current in a d-axis and q-axis synchronous rotating reference frame, the exact compensation factor was obtained. Simulations and experimental results in the low frequency and low output voltage region are presented.     

Power-efficient class AB CMOS buffer

A novel class AB unity gain voltage buffer is proposed. It is based on the use of quasi-floating gate (QFG) techniques in a super source follower topology. The circuit achieves dynamic current boosting with accurate control of quiescent currents and without penalty in supply voltage requirements or quiescent power consumption. Measurement results of the circuit, fabricated in a 0.5 mm CMOS technology, show a slew-rate enhancement by a factor 18.5 against the conventional super source follower, for the same bias current and supply voltage.     

A dead-time minimization algorithm for improving the output characteristics of the PWM inverter

The dead time in an inverter is necessary to prevent the short circuit of the DC source. However, the dead time may cause serious problems such as waveform distortion, voltage drop, increased torque ripple and heating of the motors. In this paper, a dead-time minimization algorithm is proposed for improving the inverter output performance. The adverse effects of the dead time are investigated, focusing on the voltage drop and the distortion factor of inverter output current. The proposed algorithm consists of forbidding unnecessary triggers for the inverter switches that are not turned on although the gate drive signal is impressed. The proposed algorithm is explained in terms of the conduction modes of the output currents. The validity of the proposed method is verified by comparing the simulated and experimental results with those of the conventional methods. It is concluded from the results that the proposed algorithm can reduce the output current harmonics. Further, the output voltage can be equal to the reference value and the number of inverter switchings can also be reduced to 50% compared with those of conventional methods.     

A class-B output buffer for flat-panel-display column driver

Due to the large number of output buffers on a column driver chip of a flat-panel display, the quiescent current and die area of the output buffer must be minimized. This paper presents a low static power, large output swing, and wide operating voltage range class-B output buffer amplifier for driving the large column line capacitance in a flat-panel display. A comparator is used in the negative feedback path to eliminate quiescent current in the output stage. The proposed output buffer circuit was implemented in a 0.8 μm CMOS process. Its output voltage swing is from 1 V to the supply voltage. With 5 V supply and 600 pF load, the maximum tracking error is ±7 mV. The measured static current is 24 μA. The settling time for 4 V swing to within 0.2% is 8 μs, which is more than adequate for driving 1280×1024 pixels liquid crystal displays with 86 Hz frame rate and 256 gray levels in each color     

Quaternary logic circuits in 2-μm CMOS technology

Novel quaternary logic circuits, designed in 2-μm CMOS technology, are presented. These include threshold detector circuits with an improved output voltage swing and a simple binary-to-quaternary encoder circuit. Based on these, the literal circuits, the quaternary-to-binary decoder, and the quaternary register are derived. A novel scheme for improving the power-delay product of pseudo-NMOS circuits is developed. Simulations for an inverter indicate a 66% improvement over a conventional pseudo-NMOS circuit. Noise-margin and tolerance estimations are made for the threshold detectors. To demonstrate the utility of these circuits, a quaternary sequential/storage logic array (QSLA), based on the Allen-Givone algebra has been designed and fabricated. The prototype chip occupies an area of 4.84 mm², is timed with a 2.2-MHz clock, and consumes 93 mW of power