GaAs Hall-effect devices fabricated by ion-implantation technique

Gallium-arsenide Hall-effect devices were developed by using Se-implanted n layers. A Hall voltage of 85 mV was generated at I = 1 mA and B = 5 kgauss. The imbalance voltage appearing was below 1.4 mV at I = 1 mA and B = 0.This fabrication technique is very promising in the high throughput of GaAs Hall-device production.     

High-efficiency and high-power vertical-cavity surface-emittinglaser designed for cryogenic applications

We report the first AlGaAs-GaAs vertical-cavity surface-emitting laser (VCSEL) that has been optimized for cryogenic applications near 77 K, with superior characteristics that include a high-output power (P_out=22 mW at I=25 mA), high power conversion efficiency (ηd=32%), low threshold voltage (V_th=1.75 V) and current (I_th=1.7 mA), and low power dissipation (9 mW at P_out =2.0 mW) for a 20-μm-diameter device     

高性能超低功耗的4.224GHz正交LC VCO

采用Jazz0.18μm RF CMOS工艺设计并实现应用于MB-OFDM超宽带频率综合器的4.224GHz电感电容正交压控振荡器。通过解析的方法给出了电感电容正交压控振荡器的模型,并推导出简洁的公式解释了相位噪声性能与耦合因子的关系。测试结果显示,核心电路在1.5V电源电压下,消耗6mA电流,频率调谐范围为3.566~4.712GHz;在主频频偏1MHz处的相位噪声为-119.99dBc/Hz,对应的相位噪声的FoM(Figure-of-Merit)为183dB;I、Q两路信号等效的相位误差为2.13°。     

Low power 10 GHz ring VCO using source capacitively coupled current amplifier in 0.12 /spl mu/m CMOS technology

A 10 GHz ring voltage controlled oscillator (VCO) has been designed and implemented in 0.12 /spl mu/m CMOS technology. A source capacitively coupled current amplifier (SC3A) is adopted to realise this VCO. It can operate from 8.4 GHz up to 10.6 GHz with a phase noise of about -85 dBc/Hz at 1 MHz frequency offset. With the 1.5 V supply voltage, the current consumption is about 35 mA.     

A low-power and low-phase-noise LC digitally controlled oscillator featuring a novel capacitor bank

A monolithic low-power and low-phase-noise digitally controlled oscillator(DCO) based on a symmetric spiral inductor with center-tap and novel capacitor bank was implemented in a 0.18μm CMOS process with six metal layers.A third new way to change capacitance is proposed and implemented in this work.Results show that the phase noise at 1 MHz offset frequency is below -122.5 dBc/Hz while drawing a current of only 4.8 mA from a 1.8 V supply. Also,the DCO can work at low supply voltage conditions with a 1.6 ...     

A Low‐Spur CMOS PLL Using Differential Compensation Scheme

This paper proposes LC voltage‐controlled oscillator (VCO) phase‐locked loop (PLL) and ring‐VCO PLL topologies with low‐phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer‐resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out‐band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65‐nm or 45‐nm process. The measured results of the LC‐VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of –118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring‐VCO PLL shows a phase noise of –95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.     

应用于IMT-A和UWB系统的0.13μm CMOS宽带压控振荡器设计

基于TSMC 0.13μm CMOS工艺设计并实现了应用于IMT-Advanced和UWB系统的双频段宽带频率合成器中的电感电容压控振荡器(LC-VCO)。此压控振荡器的设计采用了开关电流源、开关交叉耦合对和噪声滤波等技术,以优化电路的相位噪声,功耗,振荡幅度,调谐范围等性能。为达到宽的调谐范围,核心电路采用了4比特可重构的开关电容调谐阵列。整个芯片包括焊盘面积为1.11′0.98 mm₂。测试结果表明,在1.2V电源电压下,两个频段压控振荡器所消耗的电流分别为3mA和4.5mA,压控振荡器的调谐范围为3.86~5.28GHz和3.14~3.88GHz。在振荡频率3.5GHz和4.2GHz上,1MHz频偏处,压控振荡器的相位噪声分别为-123dBc/Hz与-119dBc/Hz。     

A Compact 3V, 70mW, 12-bit Video-Speed CMOS ADC

A 12-bit video speed pipelined switched capacitor analog-to-digitalconverter (ADC) has been implemented in a 0.5 µmstandard CMOS process. It operates from a single 2.6–;3.3Vsupply, dissipates 23mA (independent of supply voltage) at 20MSPS and occupies only 1.1mm ². A 61dB SINAD (f_in = 4.5 MHz) and an effective resolution bandwidthof 9 MHz is achieved.     

用于蓝牙收发机的低电压CMOS Gilbert混频器

对已报道的Gilbert混频器工作在低电压时存在的问题进行了分析,在此基础上,描述了利用改进的低电压设计技术,用于2.4GHz蓝牙收发机的上混频器/下混频器的设计.利用适用于低电压工作的负反馈与电流镜技术提高上混频器的线性度;而通过采用折叠级联输出,增加了低电压时下混频器的设计自由度,从而降低了噪声,提高了转换增益.基于0.35μm CMOS工艺技术,在2V电源电压下,对电路进行了仿真.结果表明:上混频器消耗的电流为3mA,输入三阶截距点达到20dBm,输出的信号幅度为87mV;下混频器消耗的电流为3.5mA,得到的转换增益是20dB,输入参考噪声电压是6.5nV/ Hz,输入三阶截距点为4.4dBm.     

192 GHz push-push VCO in 0.13 /spl mu/m CMOS

A 192 GHz cross-coupled push-push voltage controlled oscillator (VCO) is fabricated using the UMC 0.13 /spl mu/m CMOS logic process. The VCO can be tuned from 191.4 to 192.7 GHz. The VCO provides output power of /spl sim/-20 dBm and phase noise of /spl sim/-100 dBc/Hz at 10 MHz offset, while consuming 11 mA from a 1.5 V supply.     

1.3 V low close-in phase noise NMOS LC-VCO with parallel PMOS transistors

A new NMOS cross-coupled LC-VCO with parallel PMOS transistors is proposed. The proposed LC-VCO is useful for suppressing flicker noise upconversion and very suitable for low voltage application. It is implemented in 0.18 mum CMOS technology and has superior characteristics to a conventional complementary LC-VCO. Measured phase noise is -93 dBc/Hz at 100 kHz and -116 dBc/Hz at 1 MHz offsets and its core current is only 2 mA for a 1.3 V supply voltage.     

一种2.4GHz正交输出频率综合器

介绍了一种用于bluetooth的基于0.35μm CMOS工艺的2.4GHz正交输出频率综合器的设计和实现.采用差分控制正交耦合压控振荡器实现I/Q信号的产生.为了降低应用成本,利用一个二阶环路滤波器以及一个单位增益跨导放大器来代替三阶环路滤波器.频率综合器的相位噪声为-106.15dBc/Hz@1MHz,带内相位噪声小于-70dBc/Hz,3.3V电源下频率综合器的功耗为13.5mA,芯片面积为1.3mm×0.8mm.     

A coin-battery-powered LDO-Free 2.4-GHz Bluetooth Low Energy/ZigBee receiver consuming 2 mA

This paper describes a 1.5-V low dropout regulator (LDO)-free ultra-low-power 2.4-GHz CMOS receiver for direct-powering through a coin battery. By effective merging the quadrature low noise amplifier (LNA), in phase and quadrature (I/Q) mixers, a voltage controlled oscillator (VCO) and a trans-impedance amplifier (TIA) in one cell, while removing the LDO, we fully utilize the available 1.5-V voltage supply for current-reuse between blocks, minimizing the dc current consumption. Specifically, a quadrature LNA operating as both common-source and common-drain provides the I/Q outputs in the signal path. Forward-body-bias applied to the transconductance stage of the I/Q mixers relaxes their voltage headroom consumption. Prototyped in 180-nm CMOS, the receiver exhibits a conversion gain (CG) of 23 dB, a noise figure (NF) of 13.8 dB and an input-referred 3rd-order intercept point (IIP3) of −14 dBm while consuming only 2 mA. The phase noise of the VCO is −118.5 dBc/Hz at 2.5 MHz offset. The low-cost technology and low current consumption renders the receiver suitable for Internet of Things (IoT) devices using the Bluetooth Low Energy (BLE) or ZigBee standards.     

InGaAs/InP微波双极型晶体管的研制

本文叙述双收集区NpnN型InGaAs/InP异质结双极型晶体管的实验结果.给出器件的击穿特性、开关特性.高频特性和温度特性.理论分析和实验结果表明,n型InGaAs第一收集区的厚度对晶体管的击穿特性和开关特性有重要影响.器件的击穿电压BV_(CE0)=20伏,贮存时间t_s=0.5ns(Ic=50mA,I_(B1)=10mA,回抽电流I_(B2)=0),f_T=1.2GHz(V_(CE)=6V,Ic=15mA).在77～433K范围内h_(fe)变化很小,在4K下h_(fe)≌1,并表现出强烈的俄立(Early)效应.     

Low-frequency noise characteristics of p-n-p InAlAs/InGaAs HBTs

The low-frequency noise characteristics of p-n-p InAlAs/InGaAs heterojunction bipolar transistors (HBTs) were investigated. Devices with various geometries were measured under different bias conditions. The base noise current spectral density (3.11 /spl times/ 10/sup -16/ A/sup 2//Hz) was found to be higher than the collector noise current spectral density (1.48 /spl times/ 10/sup -16/ A/sup 2//Hz) at 10 Hz under low bias condition (I/sub C/=1 mA, V/sub EC/=1 V), while the base noise current spectral density (2.04 /spl times/ 10/sup -15/ A/sup 2//Hz) is lower than the collector noise current spectral density (7.87 /spl times/ 10/sup -15/ A/sup 2//Hz) under high bias condition (I/sub C/=10 mA, V/sub EC/=2 V). The low-frequency noise sources were identified using the emitter-feedback technique. The results suggest that the low-frequency noise is a surface-related process. In addition, the dominant noise sources varied with bias levels.     

A full on-chip CMOS low-dropout voltage regulator with VCCS compensation

A full on-chip CMOS low-dropout(LDO) voltage regulator with high PSR is presented.Instead of relying on the zero generated by the load capacitor and its equivalent series resistance,the proposed LDO generates a zero by voltage-controlled current sources for stability.The compensating capacitor for the proposed scheme is only 0.18 pF,which is much smaller than the capacitor of the conventional compensation scheme.The full on-chip LDO was fabricated in commercial 0.35μm CMOS technology.The active chip area...     

Design of Sub-1 mW CMOS LC VCO based on current reused topology with Q-enhancement and body-biased technique

A CMOS LC voltage controlled oscillator (VCO) based on current reused topology with low phase noise and low power consumption is presented for IEEE 802.11a (Seller et al. A 10 GHz distributed voltage controlled oscillator for WLAN application in a VLSI 65 nm CMOS process, in: IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 3–5 June, 2007, pp. 115–118.) application. The chip1 is designed with the tail current-shaping technique to obtain the phase noise −116.1 dBc/Hz and power consumption 3.71 mW at the operating frequency 5.2 GHz under supply voltage 1.4 V. The second chip of proposed VCO can achieve power consumption Sub 1 mW and is still able to maintain good phase noise. The current reused and body-biased architecture can reduce power consumption, and better phase noise performance is obtained through raising the Q value. The measurement result of the VCO oscillation frequency range is from 5.082 GHz to 5.958 GHz with tuning range of 15.8%. The measured phase noise is −115.88 dBc/Hz at 1 MHz offset at the operation frequency of 5.815 GHz. and the dc core current consumption is 0.71 mA at a supply voltage of 1.4 V. Its figure of merit (FOM) is −191 dBc/Hz. Two circuits were taped out by TSMC 0.18 μm 1P6M process.     

A 1.0 V differential VCO in 0.13 μm CMOS technology

A differential complementary LC voltage controlled oscillator(VCO) with high Q on-chip inductor is presented.The parallel resonator of the VCO consists of inversion-mode MOS(I-MOS) capacitors and an on-chip inductor.The resonator Q factor is mainly limited by the on-chip inductor.It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz.The proposed VCO is implemented in the SMIC 0.13μm 1P8M MMRF CMOS process,and the chip area is 1.0×0.8 mm~2.The free-running frequency is from 5.73 to 6.35 GHz.When oscillating at 6.35 GHz,the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is -120.14 dBc/Hz.The figure of merit of the proposed VCO is -192.13 dBc/Hz.     

Design and characterization of superlattice infrared photodetectoroperating at low bias voltage

In this paper, we investigate the performance and characterization of a 15-period superlattice embedded between two thick AlGaAs barriers. The structure can operate at low bias voltage with less power consumption for 8-10 μm long-wavelength infrared detection. In our design, one barrier is used to reduce the dark current and the other one is designed to enhance the collection efficiency of photoelectrons at the collector contact. The fabricated detector can be operated at a bias voltage lower than 0.1 V and exhibits a pronounced photovoltaic response. The spectral response shows voltage dependence around 0 V. At high bias voltage (>25 mV) the spectral lineshape is independent of bias and is around 8-10 μm with peak wavelength at 9.3 μm. At lower bias voltage the response is shifted toward shorter wavelength range. The peak responsivity was found to be 12 mA/W at λ_p =8.7 μm and zero bias and 85 mA/W at λ_p=9.3 μm and 0.1 V. Background limitation can be achieved up to 65 K with bias voltage less than 0.1 V. The measured noise power spectral density of the dark current at 77 K shows the characteristics of full shot noise rather than generation-recombination noise. The peak detectivity is determined to be D^*=3.5×10⁹ cm√(Hz)/W at 77 K and 0.1 V. In comparison with a conventional 30-period QWIP, our detector has the advantages of better performance at low bias voltages with lower power consumption and a tunable feature of spectral range     

A High-Order Temperature-Compensated Subthreshold Voltage Reference Using Channel Length Modulation Compensation Technique

The paper presents a novel high-order temperature-compensated subthreshold voltage reference that utilizes temperature characteristics of the gate-to-source voltage of subthreshold MOS transistor. The proposed high-order temperature-compensated voltage reference has been designed using two CMOS voltage references and a current subtraction circuit to achieve a low temperature coefficient over a wide temperature range. The proposed circuit offers an output reference voltage of 250.8 mV, line sensitivity of 0.0674%/V and temperature coefficient of 37.4 ppm/°C for the temperature range varying from???20 \(\mathrm{^\circ{\rm C} }\) to 140 °C at nominal conditions. The power supply rejection ratio is obtained as???46.02 dB at a frequency of 100 Hz and???41.91 dB at a frequency of 1 MHz. The proposed circuit shows an output noise of 1.86 \(\mathrm{\mu V}/\surd \mathrm{Hz}\) at 100 Hz and 259.72 \(\mathrm{nV}/\surd \mathrm{Hz}\) at 1 MHz. The proposed circuit has been designed in BSIM3V3 180 nm CMOS technology using Cadence tool. The corner analysis of the proposed circuit has also been performed to show its performance in extreme conditions. The proposed circuit occupies a small chip area of 51 \(\upmu\)m?×?75.3 \(\upmu\)m.