A bipolar device modeling technique applicable to computer-aided circuit analysis and design

The development of a modeling technique for bipolar devices is described. The application of the technique results in complete and realistic large-signal models which are amenable to computer-aided analysis. SCEPTRE has been used to effectively analyze derived models, and results of SCEPTRE analyses of a developed transistor model are presented to illustrate the general capabilities of the modeling technique and to indicate the efficiency with which the resulting models are handled by SCEPTRE. The models are structured such that systematic modifications in model complexity can be effected to reflect refinements in the states of the art of device processing and analysis, as well as to efficiently satisfy the user's model capability requirements.     

A new on-chip interconnect crosstalk model and experimentalverification for CMOS VLSI circuit design

A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is, unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-μm CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools. This model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design     

Higher order models for computer-aided circuit design

A method is presented for converting a multiple- lump transistor physical model into a combination of first-order electrical models. This conversion technique allows any higher order physical model to be implemented with the present CACD programs.     

Millimeter-wave CMOS circuit design

We have developed a 27- and 40-GHz tuned amplifier and a 52.5-GHz voltage-controlled oscillator using 0.18-mum CMOS. The line-reflect-line calibrations with a microstrip-line structure, consisting of metal1 and metal6, was quite effective to extract the accurate S-parameters for the intrinsic transistor on an Si substrate and realized the precise design. Using this technique, we obtained a 17-dB gain and 14-dBm output power at 27 GHz for the tuned amplifier. We also obtained a 7-dB gain and a 10.4-dBm output power with a good input and output return loss at 40 GHz. Additionally, we obtained an oscillation frequency of 52.5 GHz with phase noise of -86 dBc/Hz at a 1-MHz offset. These results indicate that our proposed technique is suitable for CMOS millimeter-wave design     

CMOS logic circuit optimum design for radiation tolerance

CMOS logic circuit optimum design for radiation tolerance has been investigated, based on NMOS and PMOS transistor parameter shift data due to radiation effects. The DC noise immunity for the three-input NAND has been found to be 36% greater than for the three-input NOR. The gate area for the optimised NAND is about three times smaller than that for the optimised NOR.     

A large-signal physical MESFET model for computer-aided design andits applications

A quasi-static, large-signal MESFET circuit model is presented. It is based on a comprehensive quasi-two-dimensional, semiclassical, physical device simulation, and its unique formulation and efficiency make it suitable for the computer-aided design of nonlinear MESFET subsystems. Using this approach the semiconductor equations are reduced to a consistent one-dimensional approximation requiring substantially less computing resources than a full two-dimensional simulation. CPU time is typically reduced by a factor of 1000. A single/two-tone harmonic balance analysis procedure which uses the describing frequency concept is also developed and combined with the MESFET model. Numerical load-pull contours as well as intermodulation distortion contours have been simulated; their comparison with measured results validates the approach taken     

Nonlinear J.F.E.T. model for computer-aided circuit analysis

A simplified circuit model is proposed to represent the nonlinear d.c. and low-frequency small-signal operation of j.f.e.t.s. This model is particularly useful for computer-aided circuit analysis programs, such as the iterative nodal analysis program BIAS-3. Operation in the off, resistance, and pinch-off regions of the j.f.e.t. is included.     

Physical modeling of the power VDMOST for computer-aided design ofintegrated circuit

This paper presents a methodology for physical modeling of the vertical double-diffused MOS transistor (VDMOST) for power-integrated-circuit (PIC) design. The circuit model comprises the regional models derived from basic semiconductor equations. The unique features of the VDMOST such as quasi-saturation, nonlinear inter-electrode capacitances, reverse-recovery current, and temperature dependencies are accurately modeled based on device simulations. The composite model is implemented in Saber and SPICE2G.6 source code. It is verified against steady-state and capacitance-voltage measurements on test devices. A parameter extraction routine is developed, and a system that links ICCAP and Saber is set up that performs measurement, simulation, and parameter extraction. The application of the described model in computer-aided design (CAD) is demonstrated for several power-electronic circuits     

Nonlinear large-signal modeling of transistor- collector characteristics for computer-aided circuit design

To predict large-scale collector current, a model was developed to relate collector current to base-emitter and collector-base voltages. It is similar to the Ebers-Moll model, but requires only collector characteristics to evaluate the parameters. A computer program was designed to evaluate the model for large variations in voltage, and the predicted values of I/SUB c/ agree closely with experimental data.     

TRAPATT-diode model for circuit design

A simple model of a diode operating in the TRAPATT mode is proposed which should be useful in the design of TRAPATT circuits. The model consists of only two elements; a nonlinear capacitance shunted by a voltage- and current-controlled switch. Initial simulations using this model have yielded good results without the use of excessive computer time.     

高精度CMOS带隙基准电压源电路设计

设计了一种应用于集成稳压器的高精度带隙基准电压源电路。采用共源共栅电流镜结构以及精度调节技术,有效提高了电压基准的温度稳定性和输出电压精度。经Hynix 0.5μm CMOS工艺仿真验证表明,在25℃时,温度系数几乎为零,基准电压随电源电压变化小于0.1 mV;在-40~125℃温度变化范围内,基准电压变化最大4.8 mV,满足设计指标要求。     

射频CMOS工艺中片上螺旋变压器的新型等效电路模型

本文提出一种新型的紧凑模型来模拟片上螺旋变压器的性能。传统的变压器模型一般都是两个螺旋电感模型的组合,即两个相互耦合的pi型或双pi型子电路的组合。本文所提出的新模型则采用T拓扑结构的形式,虽然它只包含12个集总元件,但是能够精确模拟整个变压器结构的特性。该新型模型具有较强的物理意义,同时文中给出了该模型的具体推导过程。另一方面,本文提出一种简单的参数提取步骤,利用这个提取步骤可以十分容易地提取出新型模型中的所有模型参数,并且不需要计算机的优化拟合。在这个提取步骤中,一个新方法被提出用来提取阶梯电路的参数,而阶梯电路被广泛用于模拟各种无源器件中的趋肤效应。为了检验该新模型的有效性和准确性,本文比较了模型仿真和实际测试在自感、品质因数、耦合系数和插入损耗等方面的特性,在自谐振频率以内的很宽频率范围内,两者均吻合得很好。     

Area efficient layout design of CMOS circuit for high-density ICs

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher I_on to I_off ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.     

A hierarchical reliability analysis for circuit design evaluation

We suggest a computationally efficient and flexible strategy for assessment of reliability of integrated circuits. The concept of hierarchical reliability analysis proposed relies on doing reliability assessments during the design and layout process [reliability computer aided design (RCAD)]. Design rules are suggested based on calculations of steady-state mechanical stresses built up in interconnect graphs and trees due to electromigration. These design rules identify a large fraction of interconnect graphs in a typical design as immune to electromigration-induced failure. The stated design rules are an extension of the Blech-length concept to interconnect graphs. Our suggested new strategy will have important implications for design and layout processes as design limits for a given technology are reached     

Equivalent circuit model of on-wafer CMOS interconnects for RFICs

This paper investigates the properties of the on-wafer interconnects built in a 0.18-/spl mu/m CMOS technology for RF applications. A scalable equivalent circuit model is developed. The model parameters are extracted directly from the on-wafer measurements and formulated into empirical expressions. The expressions are in functions of the length and the width of the interconnects. The proposed model can be easily implemented into commercial RF circuit simulators. It provides a novel solution to include the frequency-variant characteristics into a circuit simulation. The silicon-verified accuracy is proved to be up to 25 GHz with an average error less than 2%. Additionally, equivalent circuit model for longer wires can be obtained by cascading smaller subsections together. The scalability of the propose model is demonstrated.