Oxide-isolated integrated Schottky logic

Integrated Schottky logic has been fabricated in an oxide-isolated technology using 5 /spl mu/m lines and spaces. The novel device uses a merged substrate p-n-p (base width /spl sime/1.0 /spl mu/m) to clamp the collector-base junction of the oxide-walled base, down-operated n-p-n transistor. Ion-implanted low-barrier PtSi-nSi Schottky diodes are used for n-p-n collector decoupling. The average propagation delay measured on a 25-stage ring oscillator (fan-in=fan-out=1) was 2.3 ns at 65 /spl mu/A/stage and 25/spl deg/C. This 150 fJ/V power-delay product is a 3.6/spl times/ improvement compared with 540 fJ/V for junction-isolated ISL (2.7 ns at 200 /spl mu/A/stage).     

Vertical injection logic

Vertical injection logic (VIL) is a novel form of integrated injection logic (I/SUP 2/L). A vertical p-n-p transistor is used in place of a lateral p-n-p transistor to obtain an improved performance at the same packing density as conventional I/SUP 2/L. The current gain of the p-n-p transistor can be increased, which leads to the excellent power-delay product. The intrinsic delay time is also improved by the action of the bottom injector as a hole sink. The fabrication process and electrical characteristics of VIL are described and contrasted with conventional I/SUP 2/L. A tentative hole sink model is also proposed. The experimental results showed the minimum delay time of 8.8 ns and the power-delay product of 0.07 pJ at low power level below 1 /spl mu/W for VIL compared to 25 ns and 0.18 pJ for standard I/SUP 2/L.     

STL versus ISL: an experimental comparison

Schottky-transistor logic (STL) and integrated Schottky logic (ISL) have been fabricated in both 4-/spl mu/m and 2-/spl mu/m oxide isolated processes and characterized over the military temperature range (-55 to +125/spl deg/C ambient). The temperature coefficient of the average propagation delay (t/spl tilde//SUB pd/) is positive for STL over the entire operating current range. For ISL, the temperature coefficient of t/SUB pd/ is negative at low currents and positive at high currents. Both the 4-/spl mu/m and 2-/spl mu/m ring oscillator designs studied showed this behavior. At 25/spl deg/C, t/SUB pd/ data indicate no difference between STL and ISL for practical purposes. At -55/spl deg/C, the STL has a slight (~0.1 ns) speed advantage over ISL. At 150/spl deg/C (junction), the 2-/spl mu/m STL gates with a 200 /spl Omega///spl square/ base sheet resistance have the lowest minimum t/SUB pd/ of the gates studied (0.9 ns at a total current of 190 /spl mu/A) compared to the best for ISL at 1.0 ns and 150 /spl mu/A. The ISL operates at a lower logic swing than the STL at 105/spl deg/C, and has a speed advantage in the current range useful for VLSI. Additional data are presented which demonstrate the effect of the base resistance, epitaxial resistivity and substrate resistivity on delay.     

I/SUP 2/L with a self-aligned double-diffused injector

Reports the structure topology, and characterization of integrated injection logic (I/SUP 2/L/MTL) with a self-aligned double-diffused injector. It is shown that using the new structure, a lateral p-n-p transistor with effective submicron base width can be realized even by using standard photolithographic techniques. One of the features of the approach is the high injection efficiency. Another feature is the high current gain capability for n-p-n transistors. A power delay product of 0.06 pJ, a propagation delay time of 10 ns at the power dissipation of 80 /spl mu/W, and a packing density of 420 gates/mm/SUP 2/ have been obtained by single layer interconnections of 6 /spl mu/m details. A J-K flip-flop with clear and preset terminals has been fabricated to demonstrate the superiority of S/SUP 2/L to conventional I/SUP 2/L.     

Effects of gate geometry on propagation delay of integrated injection logic (I/SUP 2/L)

The effects of gate geometry on the propagation delay have been investigated for I/SUP 2/L gates with a self-aligned double-diffusion injector (S/SUP 2/L). To improve the switching speed of the I/SUP 2/L gate, the stored charge in the upside-down operated n-p-n transistor in the gate should be minimized. Following this principle, one can straightforwardly find that the reduction of the stored charges in the internal n-p-n base region and in the lateral p-n-p base region is the step to be taken for the further improvement of the speed. This can be realized by simply contracting the geometry of the gate. The minimum delay time realized in the gate was 3.2 ns/gate. Assuming that capabilities of processing the devices with 1-/spl mu/m accuracy become available, it is predicted that 1 ns/gate delay time can be realized with an improved S/SUP 2/L gate.     

A BiCMOS technology with 660-MHz vertical p-n-p transistor foranalog/digital ASICs

A fully complementary BiCMOS technology based on a 2-μm process designed for 12-V analog/digital applications is described. In this technology, a triple diffused vertical p-n-p transistor and n-p-n bipolar and CMOS devices are integrated in a single chip. A transition frequency of 660 MHz and a collector-to-emitter breakdown voltage of over 15 V have been obtained for the collector-isolated p-n-p transistor by adding only one extra mask to a conventional 2-μm BiCMOS process. The total number of masks is 20 with double-layer metallization. A unity gain frequency of 52 MHz and a DC gain of 85 dB have been obtained for a single-supply operational amplifier with a vertical p-n-p first stage. The propagation delay time for a CMOS two-NAND gate was 1.27 ns driving three loads and 3 mm of metal     

Very-low-drop voltage regulator with a fully complementary power process

A very-low-drop voltage regulator is presented that uses an isolated-collector power p-n-p transistor structure to achieve an input-output voltage drop of 0.4 V at 1 A. The device includes a circuit which prevents quiescent current peaks when the p-n-p is in saturation and a Zener-zap trimmed reference makes possible /spl plusmn/1% output voltage tolerance.     

Oxide isolated ISL technologies

Using oxide isolation, ISL gates can be fabricated without the relative slow lateral pnp transistor which is inevitable in pn-isolated processes. Now the clamping action is provided either by a fast vertical pnp only, or a reverse operated npn. Using a 1.2 µm thick epilayer and 3 µm minimum dimensions, propagation delay times of 0.7 ns are obtained at a current level of 200 µA per gate.     

High speed integrated injection logic (I/SUP 2/L)

High speed integrated injection logic (I/SUP 2/L) circuits can be manufactured in a process using oxide separation involving a very thin epitaxial layer and ion implantation. Electronic improvements which decrease the charge storage in both the p-n-p and n-p-n transistor are discussed. Analytic expressions are derived which show the consequences for the minority charge stored in the base of the n-p-n transistor and for the influences on the current noise margin. A tradeoff between noise margin and speed is then made. Besides the reduction in delay time, another attractive aspect of this approach is that it allows a simple layout design. By using separate p-n-p and n-p-n transistors, the position of the n-p-n transistors can be adapted to the logic wiring because there is no limitation in the number of crossovers. Some experimental results are given. A minimum value of the propagation delay time of 3 ns has been measured.     

Some considerations on high-speed injection logic

After a brief review of the factors that limit the switching speed of standard I/SUP 2/L, the propagation delay time of some special high-speed I/SUP 2/L gates is computed. For a gate realized in oxide-isolated, shallow epitaxial layers, the delay time is directly dependent on the injector base width. Generally, the n-p-n switching transistor hardly contributes to the time delay. For a modified I/SUP 2/L gate in which saturation of the injector is avoided, the delay time is mainly determined by the unity gain frequency of the switching transistor. However, due to the heavy saturation of this transistor, values of /spl tau//SUB d/ already realized indicate that the speed improvement is less than an order of magnitude.     

Characteristics of low-leakage deep-trench diode for ESD protection design in 0.18-/spl mu/m SiGe BiCMOS process

This paper proposes a novel low-leakage BiCMOS deep-trench (DT) diode in a 0.18-/spl mu/m silicon germanium (SiGe) BiCMOS process. By means of the DT and an n/sup +/ buried layer in the SiGe BiCMOS process, a parasitic vertical p-n-p bipolar transistor with an open-base configuration is formed in the BiCMOS DT diode. Based on the two-dimensional (2-D) simulation and measured results, the BiCMOS DT diode indeed has the lowest substrate leakage current as compared to the conventional p/sup +//n-well diode even at high temperature conditions, which mainly results from the existence of the parasitic open-base bipolar transistor. Considering the applications of the diode string in electrostatic discharge (ESD) protection circuit designs, the BiCMOS DT diode string also provides a good ESD performance. Owing to the characteristics of the low leakage current and high ESD robustness, it is very convenient for circuit designers to use the BiCMOS DT diode string in their IC designs.     

Sub-400-ps ISL circuits

This paper describes advanced Integrated-Schottky-Logic (ISL) circuits featuring double-poly self-alignment, "free" epi-base lateral p-n-p clamp, self-aligned guard ring Schottky barrier diode, and silicon-filled trench isolation. Using a 0.7-µm-thick epitaxial layer and 1.2-µm minimum dimensions, gate delays of 432 ps (fan-out = 1) and 527 ps (fan-out = 3) are obtained at current levels of 183 and 255 µA/gate, respectively; with nonwalled emitter. With walled emitter (two sides), a gate delay of 382 ps is achieved for fan-out of 3 at a current level of 267 µA/gate.     

Effects of oxide isolation on propagation delay in integrated injection logic (I/SUP 2/L)

Effects of oxide isolation on current gains, signal swing, and propagation delay time of an I/SUP 2/L gate at high dissipation levels are discussed in terms of the backward injection of the p-n-p transistor, the magnitude of which is reduced by the isolation. The reduction enhances the degree of saturation. On the other hand, it causes a larger collector current which enables a rapid discharge of the stored charge. These competing effects given an optimum condition for which the analytical expression is obtained.     

Measurement of collector and emitter resistances in bipolartransistors

New DC methods to measure the collector resistance R_C and emitter resistance R_E are presented. These methods are based on monitoring the substrate current of the parasitic vertical p-n-p transistor linked with the n-p-n intrinsic transistor. The p-n-p transistor is operated with either the bottom substrate-collector or the top base-collector p-n junction forward-biased. This allows for a separation of the various components of R_C. R_E is obtained from the measured lateral portion of R_C and the collector-emitter saturation voltage. Examples of measurements on advanced self-aligned transistors with polysilicon contacts are shown. The results show a very strong dependence of R_C on the base-emitter and base-collector voltages of the n-p-n transistor. The bias dependence of R_C is due to the conductivity modulation of the epitaxial collector. From the measured emitter resistance R_E a value for the specific contact resistance for the polysilicon emitter contact of ρ_c≅50 Ω-μm² is obtained     

An Advanced PSA Technology for High-Speed Bipolar LSI

An advanced method for polysilicon self-aligned (PSA) bipolar LSI technology has realized a miniaturized transistor for high performance. By introducing the overlapping structure for double poly-silicon electrodes, the emitter area is reduced to 1/spl mu/m X 3 /spl mu/m and the base junction is reduced to 0.3 /spl mu/m. The CML integrated circuit composed of this transistor has achieved a minimum propagation delay time of 0.29 ns/gate with power dissipation of 1.48 mW/gate. Compared to the conventional PSA method, this technology promises to fabricate higher speed and higher density LSI's.     

Gamma radiation effects on integrated injection logic cells

Integrated injection-logic (I²L) cells were tested to determine their characteristics after exposure to a total dose gamma-radiation environment. These particular devices were not designed or fabricated with radiation hardness as a goal. The common-base current gain of the lateral p-n-p transistor, the common-emitter current gain of the vertical n-p-n transistor and the forward current-voltage characteristics of the injector-substrate junction were measured over the current range of 100 nA to 300 µA as a function of dose. In addition, the propagation delay time versus power dissipation per gate at various dose levels was determined from frequency of oscillation measurements of a multiple inverter circuit.     

Characteristics of a p-n-p-n switch with an aluminum—Silicon Schottky diode clamp

An Al-Si Schottky diode has been incorporated in a p-n-p-n switch using a lateral p-n-p transistor and a vertical n-p-n transistor as a clamp. The switching characteristics are improved (speeded up). The dc characteristics display a negative resistance in the on region, and the on voltage at moderate currents is approximately the same as an unclamped p-n-p-n switch.     

Vertical charge transport and charge-handling capability injunction charge-coupled devices

In junction charge-coupled devices (JCCDs), the substrate p-n-p transistor can be applied as a versatile charge-sensing element for analog outputs, in digital circuits, and as a charge-normalizing device in optical line sensors. For all these applications, operation is controlled by clock voltage waveforms and properties of the JCCD. In particular the charge-handling capability is strongly related to vertical charge flow through the substrate p-n-p. This vertical charge transport is analyzed, showing that charge-handling capability can be defined only by taking into account vertical charge flow. Several experiments that confirm the predicted behavior is given. In addition, a method to speed up the normalization of charge packets in logic applications have been performed     

Schottky-base I/SUP 2/L: a high-performance LSI technology

A new I/SUP 2/L technology is described which offers significant advantages in packing density, device performance, and reduced LSI circuit complexity as compared to the conventional I/SUP 2/L. The basic logic gate in this design is a multiinput, multioutput NAND gate which consists of a p-n-p switch and an n-p-n injector. Schottky diodes are formed on the p-n-p base which is merged with the n-p-n (injector) collector. This I/SUP 2/L technology also offers convenient interfacing with other standard IC parts. Experimental data on a test chip indicate a p-n-p current gain of ~50, TTL-type n-p-n current gain of ~80, a delay-power product of 0.5 pJ, and a minimum delay of 10 ns for devices using 7.5 /spl mu/m minimum linewidths.     

A Parallel-Plate Waveguide Approach to Microminiaturized, Planar Transmission Lines for Integrated Circuits

The parallel-plate waveguide with a two-layer loading medium, a conducting semiconductor substrate, and a relatively thin dielectric layer approximates the interconnections in many integrated systems if the fringing fields are ignored. The fundamental mode of this structure is an E mode which is a surface wave. Its propagation behavior is analyzed in this paper and the equations are evaluated by highly accurate numerical methods. The semiconducting substrate is characterized by its dielectric constant and conductivity. A critical conductivity /spl sigma//sub min/ exists and is related to the cross sectional and material parameters. If the substrate conductivity is given by /spl sigma//sub min/ then the attenuation constant of the line is a minimum. The same value of conductivity yields minimum phase distortion at maximum bandwidth. If the conductivity is larger than /spl sigma//sub min/ the substrate acts as a poor conductor with associated skin effect; if it is smaller, lossy dielectric behavior results. Analysis shows that it is appropriate to subdivide the frequency range into three intervals. The lowest-frequency interval is characterized by propagation which resembles diffusion. This is caused by the loss in the dielectric layer. The next frequency range extends to some upper frequency which is determined by substrate conductivity and the cross-sectional dimensions. In this interval, the phase velocity of the fundamental mode is controlled by the ratio of dielectric to semiconductor thickness, which, if typical interconnections are considered, implies a very low velocity. This property indicates that the structure can serve as a delay line. Further increases in frequency result in higher phase velocities. Skin effect and dielectric loss behavior describe the propagation in this third interval.