A fully operational 1-kbit HEMT static RAM

In this paper we describe the current status of materials and fabrication technologies, and optimal design of a memory cell, and the performance of fully functional 1-kbit HEMT SRAM's. The surface defect density on MBE-grown wafers has been reduced to less than 100 cm^-2by improving MBE technology. Standard deviations of threshold voltages are 6.7 and 11.8 mV for enhancement-type and depletion-type HEMT's, respectively, measured in a 10 mm × 10 mm area. These deviations are sufficiently small for DCFL circuits. Memory cell design parameters have been optimized by circuit simulation, where the effects of variations in threshold voltages are taken into account. Full function of 1-kbit SRAM's has been confirmed by marching tests and partial galloping tests. The RAM chips have also shown excellent uniformity in access time. The difference between maximum and average values on the RAM chip is 4 percent.     

An ECL-compatible GaAs MESFET 1-kbit static RAM

A fully ECL-compatible GaAs enhancement/depletion (E/D)-MESFET 1-kb static RAM was designed, fabricated, and tested. Direct-coupled FET logic is used for the memory array while buffered FET logic is utilized in the peripheral circuitry to provide an ECL 100 K interface. The memory cell area is 774 /spl mu/m/SUP 2/, and the chip size is 2.0/spl times/1.75 mm/SUP 2/. Fabrication of the 1-kb RAM involves a fully implanted two-threshold process with true double-level metal interconnection. A minimum access time of 1.3 ns has been obtained with a total power dissipation of 1.4 W (memory array power dissipation is only ~40 mW). The output voltage swing across a 50-/spl Omega/ load is 750 mV.     

A GaAs 16-kbit static RAM using dislocation-free crystal

A GaAs 16-kbit static RAM was developed using high-density integration technology and high-uniformity crystal. Highly integrated SAINT FET's with 1.0-µm gate length and 1.5-µm interconnection lines were formed by self-alignment and fine photolithography. Highly uniform crystal with less than 20-mV threshold scattering was obtained from an In-doped dislocation-free LEC with a 2-in diameter. An address access time of 4.1 ns was obtained with an associated power dissipation of 1.46 W.     

A traveling-wave high electron mobility transistor

A traveling-wave high electron mobility transistor (THEMT) is proposed. The device is unique in that it includes an integral distributed load resistor and uses a HEMT as the active device. A rigorous analysis of the device is carried out, using a small-signal equivalent circuit model for an incremental section of the device. Losses and reflected waves are not neglected, as has been done in other work. Treating the device as a four-port network, closed-form expressions for S-parameters are derived. Theoretical calculations, using equivalent circuit parameter values for a HEMT reported in the literature, show that the proposed device is capable of exponential increase in gain with device width. Power gain of more than 10 dB at 50 GHz and remarkably flat response in the frequency range 10-100 GHz are shown to be achievable for a 1-mm-wide device     

A GaAs 1-kbit static RAM with a shallow recessed-gate structure FET

A novel GaAs FET structure, the shallow recessed-gate structure, has been proposed and applied to a 1-kbit static RAM. In order to decrease the source resistance Rsand gate capacitance Cg, the shallow n⁺implanted layer was formed between the gate and source/drain region; then the gate region was slightly recessed. This FET has a high transconductance gm, low source resistance Rs, small gate capacitance Cg, and small deviation of threshold voltagepart V_{th}, and thus is suitable for high-speed GaAs LSI's. A 1-kbit static RAM has been designed and fabricated applying this FET structure and an access time of 3.8 ns with 38- mW power dissipation has been obtained.     

A 0.85-ns 1-kbit ECL RAM

A 1-kb ECL RAM with an address access time of 0.85 ns is described. This excellent performance is achieved by combining super self-aligned technology (SST) with 1-/spl mu/m design rules and high-speed circuit design. SST provides a narrow emitter stripe width of 0.5 /spl mu/m and a high cutoff frequency of 12.4 GHz at V/SUB CE/=3 V. A two-level metallization process is used. The minimum metallization pitches are 3 /spl mu/m in the first layer and 6 /spl mu/m in the second one. The chip size is 2.5/spl times/2.5 mm/SUP 2/ and the power dissipation is 950 mW. This RAM is promising for use in super computers and/or high-speed digital systems.     

A microwave power double-heterojunction high electron mobility transistor

A microwave power high electron mobility transistor (HEMT) has been developed and tested in theK-band frequency range. The HEMT has a unique configuration of a selectively low-doped (AlGa)As/GaAs/(AlGa)As double heterojunction resulting in both capability of high-current density and high gate breakdown voltage. The structure showed electron mobility of 6800 cm²/V.s and two-dimensional (2-D) electron density as high as 1.2 × 10¹²cm^-2at room temperature. An output power of 660 mW (550 mW/mm) with 3.2-dB gain and 19.3-percent power added efficiency was achieved at 20 GHz with 1-µm gate length and 1.2-mm gate periphery. A similar device with 2.4-mm gate width produced an output power of 1 W with 3-dB gain and 15.5-percent efficiency. These results offer microwave high power capability in a double-heterojunction HEMT (DH-HEMT).     

A high-speed Hi-CMOSII 4K static RAM

Using advanced high-performance CMOS (Hi-CMOSII) technology and a high-speed circuit technique, a fully static 4096-word by one-bit RAM with typical address access time of 18 ns and power dissipation of 150 mW has been designed. The power-access-time product realized by the design is almost an order of magnitude better than existing NMOS 4K static RAMs. Moreover, to produce low-cost high-density static RAMs, a new redundancy technique utilizing laser shorting of intrinsic polysilicon is proposed.     

GaAs E/D MESFET 1-kbit static RAM fabricated on silicon substrate

A GaAs enhancement/depletion (E/D) MESFET 1-kbit static RAM has been fabricated on a 2-in GaAs-on-Si substrate. This is the most complex GaAs circuit reported to date for GaAs-on-Si material. The GaAs layer is grown on a     

高电子迁移率晶体管新结构

介绍了通过插入ＩｎＡｓ层到ＩｎＧａＡｓ沟道中，改善了ＩｎＡｌＡｓ／ＩｎＧａＡｓ高电子迁移率晶体管（ＨＥＭＴ）的性质，合适的ＩｎＡｓ层厚度和准确的插入位置会使在３００Ｋ时此结构的ＨＥＭＴ比普通结构的ＨＥＭＴ的迁移率和电子速度分别提高３０％和１５％。     

A 64-kbit dynamic MOS RAM

A 64-kbit dynamic MOS RAM is developed by using 2 /spl mu/m rule VLSI fabrication technology and low power circuit technology. The 2 /spl mu/m rule VLSI fabrication technology is achieved by improving various aspects of the ultraviolet photolithographic, thin-gate oxidation, arsenic ion implantation, and multilevel interconnection processes. Microminiaturization of the device structure has made the voltage requirements for its MOST threshold voltage and DC supply voltages low. A highly sensitive and low power dissipating sense circuit has been developed for the VLSI RAM. A new level-detecting circuit with a logic threshold which is independent of MOST threshold voltage is proposed. A dynamic address-buffer circuit is also shown. The fabricated 64K RAM has 200 ns of access time, 370 ns of minimum cycle time, and 150 mW of power dissipation under typical supply voltage conditions of V/SUB DD/=7 V and V/SUB BB/=-2 V.     

A high-speed low-power Hi-CMOS 4K static RAM

A high-speed low-power CMOS fully static, 4096 word by 1 bit random-access memory (RAM) has been developed, which contains a bipolar-CMOS (BCMOS) circuit on the same chip. The device is realized using low-power-oriented circuit design and high-performance CMOS technology utilizing 3-µm gate length. The fabricated 4K static RAM has an address access time of 43 ns and a power dissipation of 80 mW.     

A High-Speed 64-kbit CMOS RAM

The first memory of a high-performance CMOS 64K family, an 8K X 8 asynchronous static RAM, has been developed using a full CMOS six-transistor memory cell approach to reduce power consumption and enhance endurance in disturbed environments. New design techniques have been adopted to optimize both speed and power dissipation. Built on a self-aligned CMOS technology with 1.5-/spl mu/m design rules, the circuit reaches the size of 45 mm/sup 2/ and achieves access times of 35 ns under typical conditions. To improve fabrication yield of the memory, redundancy assistance has been utilized allowing correction of physical defects by column replacement.     

Quarter-micron gate length microwave high electron mobility transistor

Quarter-micron gate length high electron mobility transistors have been fabricated using an electron-beam direct-writing technique. A maximum stable gain of 10 dB at 18 GHz has been measured at room temperature. A room-temperature cutoff frequency fT as high as 45 GHz has also been obtained.     

A 40-ps high electron mobility transistor 4.1 K gate array

A high-electron mobility transistor (HEMT) 4.1 K-gate array has been developed, using a selective dry etching process and a MBE (molecular-beam epitaxy) growth technology. The circuit design uses direct-coupled FET logic (DCFL). The chip contains 4096 NOR gates, each with a 0.8-μm gate length, and measures 6.3 mm×4.8 mm. A basic gate delay of 40 ps has been achieved. A 16×16-bit parallel multiplier, used to test this array, has a multiplication time of 4.1 ns at 300 K, where the power dissipation is 6.2 W     

A 1.0-ns 5-kbit ECL RAM

A bipolar 512/spl times/10-bit emitter-coupled logic (ECL) RAM with an access time of 1.0 ns and a power dissipation of 2.4 W, achieving an access-time power/bit product of 0.48 pJ/bit, has been developed. The RAM was fabricated using an advanced bipolar technology featuring poly-base self-alignment, poly-emitter shallow profile, and silicon-filled trench isolation with a minimum mask dimension of 1.2 /spl mu/m. A Schottky-clamped multiemitter cell with a cell size of 760 /spl mu/m/SUP 2/ is obtained as a result of compact cell layout and the use of 1.2-/spl mu/m trench isolation.     

Two-dimensional numerical analysis of the high electron mobility transistor

We develop a two-dimensional model for the high electron mobility transistor (HEMT) including conduction outside the quantum well. The model uses the continuity and power balance moment equations for both inside and outside the well, with electron concentration and average energy as dependent variables, and with parameters determined by Monte Carlo simulation. We show that conduction outside the well is dominant in the "pinchoff" region and that consequently the speed advantage of the HEMT over conventional devices does not arise from high saturation velocities in the quantum well but rather from a lower access resistance as suggested by a velocity profile calculation. It is further demonstrated that several effects which are unimportant in conventional FET's are of significance in the HEMT. Among these effects are electronic heat conduction and to some extent real space transfer.     

A 3-ns 1-kbit RAM using super self-aligned process technology

A high speed 1-kbit ECL RAM with a typical access time of 2.7 ns and power dissipation of 500 mW has been developed, using a novel LSI fabrication process technology, together with a new reference circuit configuration. This paper describes an integrated transistor structure using this novel process technology, fabrication steps, a new sense circuit and performance of the RAM.     

Circuit simulation models for the high electron mobility transistor

A three-terminal model is formulated for the high electron mobility transistor (HEMT) using charge-voltage relationships derived from the Boltzmann transport. Emphasis is placed on modeling the current transport of the two-dimensional electron gas (TEG) and the capacitance of the embedded parasitic MESFET structure. Furthermore, a distributed circuit topology is used to better model high-frequency effects, such as the transit time delay, in both small-signal and large-signal-transient analysis. The HEMT model is implemented in the circuit simulation program HP-SPICE. Both dc and ac simulation results are discussed.     

Two-dimensional numerical model for the high electron mobility transistor

A two-dimensional numerical drift-diffusion model for the High Electron Mobility Transistor (HEMT) is presented. Special attention is paid to the modeling of the current flow over the heterojunction. A finite difference scheme is used to solve the equations, and a variable mesh spacing was implemented to cope with the strong variations of functions near the heterojunction. Simulation results are compared to experimental data for a 0.7 μm gate length device. Small-signal transconductances and cut-off frequency obtained from the 2-D model agree well with the experimental values from S-parameter measurements. It is shown that the numerical models give good insight into device behaviour, including important parasitic effects such as electron injection into the bulk GaAs.