A sensitivity and linearity improvement of a 100-dB dynamic range CMOS image sensor using a lateral overflow integration capacitor

In a CMOS image sensor featuring a lateral overflow integration capacitor in a pixel, which integrates the overflowed charges from a fully depleted photodiode during the same exposure, the sensitivity in nonsaturated signal and the linearity in saturated overflow signal have been improved by introducing a new pixel circuit and its operation. The floating diffusion capacitance of the CMOS image sensor is as small as that of a four transistors type CMOS image sensor because the lateral overflow integration capacitor is located next to the reset switch. A 1/3-inch VGA format (640/sup H//spl times/480/sup V/ pixels), 7.5/spl times/7.5 /spl mu/m/sup 2/ pixel color CMOS image sensor fabricated through 0.35-/spl mu/m two-poly three-metal CMOS process results in a 100 dB dynamic range characteristic, with improved sensitivity and linearity.     

Crosstalk and microlens study in a color CMOS image sensor

The paper describes results of crosstalk investigations and microlens (/spl mu/-lens) scan experiments in a color CMOS image sensor with active pixel structure . The investigation of optical and electrical crosstalk was made on 7.8- and 5.6-/spl mu/m pixels by using samples with continuous shift of color filter (CF ) and /spl mu/-lens across the array. As a result of this investigation, the distribution of sensitivity inside a pixel has been determined. By using minimum crosstalk criteria, the optimum parameters of the /spl mu/-lens manufacturing process and optimum position of the /spl mu/-lens was determined. The paper presents color maps of pixel sensitivity and crosstalk criteria as well as snapshots illustrating sensitivity distribution and collection area. The paper presents spectral characteristics measured at different relative apertures (f-number) as well. The quantitative analysis of spectral responses allowed us to determine the contribution of each component to the overall crosstalk.     

A 0.18-/spl mu/m CMOS bioluminescence detection lab-on-chip

The paper describes a bioluminescence detection lab-on-chip consisting of a fiber-optic faceplate with immobilized luminescent reporters/probes that is directly coupled to an optical detection and processing CMOS system-on-chip (SoC) fabricated in a 0.18-/spl mu/m process. The lab-on-chip is customized for such applications as determining gene expression using reporter gene assays, determining intracellular ATP, and sequencing DNA. The CMOS detection SoC integrates an 8 /spl times/ 16 pixel array having the same pitch as the assay site array, a 128-channel 13-bit ADC, and column-level DSP, and is fabricated in a 0.18-/spl mu/m image sensor process. The chip is capable of detecting emission rates below 10/sup -6/ lux over 30 s of integration time at room temperature. In addition to directly coupling and matching the assay site array to the photodetector array, this low light detection is achieved by a number of techniques, including the use of very low dark current photodetectors, low-noise differential circuits, high-resolution analog-to-digital conversion, background subtraction, correlated multiple sampling, and multiple digitizations and averaging to reduce read noise. Electrical and optical characterization results as well as preliminary biological testing results are reported.     

A high-efficiency CMOS image sensor with air gap in situ MicroLens (AGML) fabricated by 0.18-/spl mu/m CMOS technology

The air gap in situ microlens (AGML) above-pixel sensor with 0.18-/spl mu/m CMOS image sensor technology has been successfully developed to dramatically improve the optical crosstalk and pixel sensitivity. We demonstrated excellent crosstalk diminution with the structure on small pixels. Compared with conventional 2.8 /spl mu/m square pixel, adopting the AGML can reduce the optical crosstalk up to 64%, and provide 21% in enhancement of photosensitivity at 0/spl deg/ incident angle. Furthermore, under 20/spl deg/ incident angle the optical crosstalk reduction and sensitivity enhancement are increased to 89% and 122%, respectively. Therefore, the AGML structure makes pixel size be further scaled down to less than 2.8 /spl mu/m square and maintain good performance.     

Novel current-mode background suppression for 2-D LWIR applications

A new readout circuit involving two-step current-mode background suppression is studied for two-dimensional long-wavelength infrared focal plane arrays (2-D LWIR FPAs). Buffered direct injection (BDI) and a feedback amplifier are used for the input circuit and background suppression circuit, respectively. The readout circuit has been fabricated using a 0.6-/spl mu/m 2-poly 3-metal CMOS process for a 64/spl times/64 LWIR HgCdTe IR array with a pixel size of 50 /spl mu/m/spl times/50 /spl mu/m. The simple pixel circuit has a very small skimming error of less than 0.3% and low noise characteristics for an adequate calibration range and integration time.     

Light guide for pixel crosstalk improvement in deep submicron CMOS image sensor

Light guide, a novel dielectric structure consisting of PE-Oxide and FSG-Oxide, has been developed to reduce crosstalk in 0.18-/spl mu/m CMOS image sensor technology. Due to the difference in refraction index (1.46 for PE-Oxide and 1.435 for FSG-Oxide), major part of the incident light can be totally reflected at the interface of PE-Oxide/FSG-Oxide, as the incidence angle is larger than total reflection angle. With this light guide, the pixel sensing capability can be enhanced and to reduce pixel crosstalk. Small pixels with pitch 3.0-/spl mu/m and 4.0-/spl mu/m have been characterized and examined. In 3.0-/spl mu/m pixel, optical crosstalk achieves 30% reduction for incidence angle of light at 10/spl deg/.     

A biomorphic digital image sensor

An arbitrated address-event imager has been designed and fabricated in a 0.6-/spl mu/m CMOS process. The imager is composed of 80 /spl times/ 60 pixels of 32 /spl times/ 30 /spl mu/m. The value of the light intensity collected by each photosensitive element is inversely proportional to the pixel's interspike time interval. The readout of each spike is initiated by the individual pixel; therefore, the available output bandwidth is allocated according to pixel output demand. This encoding of light intensities favors brighter pixels, equalizes the number of integrated photons across light intensity, and minimizes power consumption. Tests conducted on the imager showed a large output dynamic range of 180 dB (under bright local illumination) for an individual pixel. The array, on the other hand, produced a dynamic range of 120 dB (under uniform bright illumination and when no lower bound was placed on the update rate per pixel). The dynamic range is 48.9 dB value at 30-pixel updates/s. Power consumption is 3.4 mW in uniform indoor light and a mean event rate of 200 kHz, which updates each pixel 41.6 times per second. The imager is capable of updating each pixel 8.3K times per second (under bright local illumination).     

A pixel-level automatic calibration circuit scheme for capacitive fingerprint sensor LSIs

We propose a pixel-level automatic calibration circuit scheme that initializes a capacitive fingerprint sensor LSI to eliminate the influence of the surface condition, which is degraded by dirt during long-time use. The scheme consists of an automatic calibration circuit for each pixel and a calibration control circuit for the pixel array. The calibration is executed by adjusting variable capacitance in each pixel to make the sensor signals of all pixels the same. The calibration control circuit selects the pixels in parallel, and calibrates all pixels in a short time. The scheme was applied to a fingerprint sensor LSI using the 0.5-/spl mu/m CMOS process/sensor process, and clear fingerprint images were obtained even for a degraded surface condition. This confirms that the scheme is effective for capturing consistent clear images during long-time use.     

CMOS image sensor with mixed-signal processor array

We present a single-chip integration of a CMOS image sensor with an embedded flexible processing array and dedicated analog-to-digital converter. The processor array is designed to perform convolution and transformation algorithms with arbitrary kernels. It has been designed to carry out the multiplication of analog image data with given digital kernel coefficients and to add up the results. The processor array is an analog implementation of a highly parallel architecture which is scalable to any desired sensor resolution while preserving video-rate operation. A prototype implementation has been realized in a 0.6-/spl mu/m CMOS technology. Switched current technique has been applied to obtain compact and robust circuits. The prototype's sensor resolution is 64 /spl times/ 128 pixels. The processor array occupies a small chip area and consumes only a small percentage of the power (250 /spl mu/W) of the whole image sensor.     

Prediction of CMOS APS design enabling maximum photoresponse for scalable CMOS technologies

This brief represents the CMOS active pixel sensor (APS) photoresponse model use for maximum pixel photosignal prediction in scalable CMOS technologies. We have proposed a simple approximation determining the technology-scaling effect on the overall device photoresponse. Based on the above approximation and the data obtained from the CMOS 0.5 /spl mu/m process thorough investigation we have theoretically predicted, designed, measured and compared the optimal (in the output photosignal sense) pixel in a more advanced, CMOS 0.35 /spl mu/m technology. Comparison of both, our theoretically predicted and modeled results and the results obtained from the measurements of an actual pixel array gives excellent agreement. It verifies the presented scaling-effect approximation and validates the usefulness of our model for design optimization in scalable CMOS technologies.     

Modeling of the bulk versus SOI CMOS performances for the optimal design of APS circuits in low-power low-voltage applications

In this paper, we present the top-down design of an active pixel sensor (APS) circuit using an analytical model of its architecture. The model is applied to compare the performances of bulk versus silicon-on-insulator (SOI) CMOS processes and devices on the designs and performance of several 50-frames/s imagers in 2-/spl mu/m and 0.25-/spl mu/m CMOS with different pixels array sizes. For 2-/spl mu/m SOI, results show a reduction by two of the power consumption and a dynamic range increase of 0.85 V under a 3-V supply. This results in an SNR of 79 dB instead of 76. Fixed pattern noise (FPN) is also reduced from 2.7 to 1.8 mV which represents 0.26% and 0.08% of the dynamic range, respectively. For 0.25-/spl mu/m CMOS SOI, results show a reduction by 6.5 of the power consumption, FPN more than five time better, and a dynamic range increase of 0.29 V under a 1.5-V supply. However, because of the increase of the thermal noise due to the particular design choice, an SNR of 60.3 dB is achieved compared to 63 in bulk. A better SNR in SOI than in bulk can be achieved but at the expense of power consumption and FPN. However, this could be combined with an increase in pixels number in SOI compared to bulk. Potential results achievable in SOI have to our knowledge never been reached by bulk APS imagers up to now.     

Adaptive-integration-time image sensor with real-time reconstruction function

A computational image sensor is proposed in which the pixel controls its integration time to light intensity. The integration time of each pixel is selected from among several lengths of integration time and the integration time is shortened if the pixel intensity becomes saturated. Although the integration time of each pixel varies, the pixel intensity is adjusted on the sensor in real time. The dynamic range of the pixel value output from the proposed sensor is greatly widened. A prototype of 64/spl times/48 pixels has been fabricated by using 2-poly 2-metal 0.8-/spl mu/m CMOS process. The proposed sensor has simple functions for the comparison of intermediate integration value and threshold to control the integration time and nonlinear image reconstruction. Because the maximum number of the comparison-reset operations during a frame is three, one of the four integration times can be selected pixel by pixel. The circuit and layout design of the prototype which has computational elements based on column parallel architecture are described and the fundamental functions have been verified. By the experiments, it has been verified that the sensor can achieve a wide dynamic range by adapting to light.     

Multiple integration method for a high signal-to-noise ratio readout integrated circuit

A multiple integration method is reported that greatly improves the signal-to-noise ratio (SNR) for applications with a high-resolution infrared (IR) focal plane array. The signal from each pixel is repeatedly sampled into an integration capacitor and then output and summed into an outside memory that continues for n read cycles during each period of a frame. This method increases the effective capacity of the charge integration and improves sensitivity. Because a low-noise function block and high-speed operation of the readout circuit is required, a new concept is proposed that enables the readout circuit to perform digitization by a voltage skimming method. The readout circuit was fabricated using a 0.6-/spl mu/m CMOS process for a 64/spl times/64 midwavelength IR HgCdTe detector array. The readout circuit effectively increases the charge storage capacity to 2.4/spl times/10/sup 8/ electrons and then provides a greatly improved SNR by a factor of approximately 3.     

A new CMOS pixel structure for low-dark-current and large-array-size still imager applications

A pixel structure for still CMOS imager application called the pseudoactive pixel sensor (PAPS) is proposed and analyzed in this paper. It has the advantages of a low dark current, high signal-to-noise ratio, and a high fill factor over the conventional passive pixel sensor imager or active pixel sensor imager. The readout circuit called the zero-bias column buffer-direct-injection structure is also proposed to suppress both the dark current of the photodiode and the leakage current of row switches by keeping both biases of photodiode and the parasitic p-n junction in the column bus at or near zero voltage. The improved double delta sampling circuits are also used to suppress fixed pattern noise, clock feedthrough noise, and channel charge injection. An experimental chip of the proposed PAPS CMOS imager with the format of 352/spl times/288 (CIF) has been fabricated by using a 0.25-/spl mu/m single-poly-five-level-metal (1P5M) n-well CMOS process. The pixel size is 5.8 /spl mu/m/spl times/5.8 /spl mu/m. The pixel readout speed is from 100 kHz to 10 MHz, corresponding to the maximum frame rate above 30 frames/s. The proposed still CMOS imager has a fill factor of 58%, chip size of 3660 /spl mu/m/spl times/3500 /spl mu/m, and power dissipation of 24 mW under the power supply of 3.3 V. The experimental chip has successfully demonstrated the function of the proposed new PAPS structure. It can be applied in the design of large-array-size still CMOS imager systems with a low dark current and high resolution.     

A 9-V/Lux-s 5000-frames/s 512/spl times/512 CMOS sensor

A high-responsivity 9-V/Lux-s high-speed 5000-frames/s (at full 512/spl times/512 resolution) CMOS active pixel sensor (APS) is presented in this paper. The sensor was designed for a 0.35-/spl mu/m 2P3M CMOS sensor process and utilizes a five-transistor pixel to provide a true parallel shutter. Column-parallel analog-to-digital converter (ADC) architecture yields fast readout from pixels and digitization of the data simultaneously with acquiring a new frame. The chip has a two-row SRAM to store data from the ADC and read previous rows of data out of the chip. There are a total of 16 parallel ports operating up to 90 MHz delivering /spl sim/1.3 Gpixel/s or 13 Gb/s of data at the maximum rate. In conclusion, a comparison between two high-speed digital CMOS sensor architectures, which are a column-parallel APS and a digital pixel sensor (DPS), is conducted.     

PWM digital pixel sensor based on asynchronous self-resetting scheme

In this letter, a pulse-width modulated digital pixel sensor is presented along with its inherent advantages such as low power consumption and wide operating range. The pixel, which comprises an analog processor and an 8-bit memory cell, operates in an asynchronous self-resetting mode. In contrast to most CMOS image sensors, in our approach, the photocurrent signal is encoded as a pulse-width signal, and converted to an 8-bit digital code using a Gray counter. The dynamic range of the pixel can be adapted by simply modulating the clock frequency of the counter. To test the operation of the proposed pixel architecture, an image sensor array has been designed and fabricated in a 0.35-/spl mu/m CMOS technology, where each pixel occupies an area of 45/spl times/45 /spl mu/m/sup 2/. Here, the operation of the sensor is demonstrated through experimental results.     

A digital pixel sensor array with programmable dynamic range

This paper presents a digital pixel sensor (DPS) array employing a time domain analogue-to-digital conversion (ADC) technique featuring adaptive dynamic range and programmable pixel response. The digital pixel comprises a photodiode, a voltage comparator, and an 8-bit static memory. The conversion characteristics of the ADC are determined by an array-based digital control circuit, which linearizes the pixel response, and sets the conversion range. The ADC response is adapted to different lighting conditions by setting a single clock frequency. Dynamic range compression was also experimentally demonstrated. This clearly shows the potential of the proposed technique in overcoming the limited dynamic range typically imposed by the number of bits in a DPS. A 64 /spl times/ 64 pixel array prototype was manufactured in a 0.35-/spl mu/m, five-metal, single poly, CMOS process. Measurement results indicate a 100 dB dynamic range, a 41-s mean dark time and an average current of 1.6 /spl mu/A per DPS.     

Dramatic reduction of optical crosstalk in deep-submicrometer CMOS imager with air gap guard ring

A dielectric structure, air gap guard ring, has been successfully developed to reduce optical crosstalk thus improving pixel sensitivity of CMOS image sensor with 0.18-/spl mu/m technology. Based on refraction index (RI) differences between dielectric films (RI = 1.4 /spl sim/ 1.6) and air gap (RI = 1), total internal reflection occurred at dielectric-film/air-gap interface, thus the incident light is concentrated in selected pixel. Excellent optical performances have been demonstrated in 3.0 /spl times/ 3.0 /spl mu/m pixel. Optical spatial crosstalk achieves 80% reduction at 20/spl deg/ incidence angle and significantly alleviates the pixel sensitivity degradation with larger angle of incident light.     

A 1/3' VGA linear wide dynamic range CMOS image sensor implementing a predictive multiple sampling algorithm with overlapping integration intervals

Many tasks performed by machine vision systems involve processing of natural scenes with large intra-frame illumination ratios. Thus, wide dynamic range visible spectrum image sensors are required to achieve adequate processing performance and reliability. An image sensor implementing an algorithm that linearly increases the illumination dynamic range of solid-state pixels is presented. Optimal exposure is achieved with a predictive pixel saturation decision that allows for multiple integration intervals of different duration to run concurrently for different pixels while keeping the sensor frame rate constant. A proof-of-concept chip was fabricated in a 0.18-/spl mu/m CMOS process. Added functionality to standard imagers is mainly concentrated off-pixel so fill factor is not sacrificed. Measured data corroborates the algorithm functionality.