Thin-film transistors in polycrystalline silicon by blanket andlocal source/drain hydrogen plasma-seeded crystallization

Thin film n-channel transistors have been fabricated in polycrystalline silicon films crystallized using hydrogen plasma seeding, by using several processing techniques with 600 to 625°C or 1000°C as the maximum process temperature. The TFTs from hydrogen plasma-treated films with a maximum process temperature of 600°C, have a linear field-effect mobility of ~35 cm²/Vs and an ON/OFF current ratio of ~10⁶, and TFTs with a maximum process temperature of 1000°C, have a linear field-effect mobility of ~100 cm²/Vs and an ON/OFF current ratio of ~10⁷. A hydrogen plasma has also then been applied selectively a in the source and drain regions to seed large crystal grains in the channel. Transistors made with this method with maximum temperature of 600°C showed a nearly twofold improvement in mobility (72 versus 37 cm² /Vs) over the unseeded devices at short channel lengths. The dominant factor in determining the field-effect mobility in all cases was the grain size of the polycrystalline silicon, and not the gate oxide growth/deposition conditions. Significant increases in mobility are observed when the grain size is in order of the channel length. However the gate oxide plays an important role in determining the subthreshold slope and the leakage current     

An investigation of laser annealed and metal-induced crystallizedpolycrystalline silicon thin-film transistors

We report results on thin-film transistors (TFTs) made from a new hybrid process in which amorphous silicon (a-Si) is first converted to polycrystalline silicon (poly-Si) using Ni-metal-induced lateral crystallization (MILC), and then improved using excimer laser annealing (laser MILC or L-MILC). With only a very low shot laser process, we demonstrate that laser annealing of MILC material can improve the electron mobility from 80 to 170 cm²/Vs, and decrease the minimum leakage current by one to two orders of magnitude at a drain bias of 5 V. Similar trends occur for both p- and n-type material. A shift in threshold voltage upon laser annealing indicates the existence of a net positive charge in Ni-MILC material, which is neutralised upon laser exposure. The MILC material in particular exhibits a very high generation state density of ~10¹⁹ cm^-3 which is reduced by an order of magnitude in L-MILC material. The gate and drain field dependences of leakage current indicate that the leakage current in MILC transistors is related to this high defect level and the abruptness of the channel/drain junction. This can be improved with a lightly doped drain (LDD) implant, as in other poly-Si transistors     

High performance poly-Si TFTs fabricated using pulsed laserannealing and remote plasma CVD with low temperature processing

Key technologies for fabricating polycrystalline silicon thin film transistors (poly-Si TFTs) at a low temperature are discussed. Hydrogenated amorphous silicon films were crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Crystalline grains were smaller than 100 nm. The density of localized trap states in poly-Si films was reduced to 4×10¹⁶ cm^-3 by plasma hydrogenation only for 30 seconds. Remote plasma chemical vapor deposition (CVD) using mesh electrodes realized a good interface of SiO ₂/Si with the interface trap density of 2.0×10¹⁰ cm^-2 eV^-1 at 270°C. Poly-Si TFTs were fabricated at 270°C using laser crystallization, plasma hydrogenation and remote plasma CVD. The carrier mobility was 640 cm²/Vs for n-channel TFTs and 400 cm²/Vs for p-channel TFTs. The threshold voltage was 0.8 V for n-channel TFTs and -1.5 V for p-channel TFTs. The leakage current of n-channel poly-Si TFTs was reduced from 2×10^-10 A/μm to 3×10^-13 A/μm at the gate voltage of -5 V using an offset gate electrode with an offset length of 1 μm     

High field effect mobility deuterated amorphous silicon thin-filmtransistors based on the substitution of hydrogen with deuterium

The characteristics of amorphous silicon hydrogen and deuterium thin-film transistors (a-Si:H/a-Si:D TFT) were studied. The deuterated and hydrogenated amorphous silicon channels were prepared by first annealing the as-deposited a-Si:H layer at 550°C in N₂ environment to expel all the hydrogen atoms out of the films, then the D ₂ or H₂ plasma were applied to treat the amorphous silicon layers. The field effect mobility of the conventional hydrogen TFT is usually smaller than 1 cm²/V-s. It was found that substitution of hydrogen with deuterium improved the field effect mobility of the TFT. The maximum field effect mobility of a-Si:D TFT obtained from the saturation region was 1.77 cm²/V-s     

Amorphous silicon buried-channel thin-film transistors

We demonstrate a buried-channel thin-film field effect transistor (TFT) based on deposited silicon nitride and hydrogenated amorphous silicon with the conducting channel recessed approximately 50 Å from the interface. We fabricate transistors and capacitors by DC reactive magnetron sputtering of a silicon target in a plasma of (Ar+H ₂+N₂) or (Ar+H₂) for the nitride and silicon layers, respectively. To create a step in the conduction band, and thus a buried-channel, we vary the hydrogen partial pressure which varies the hydrogen content and the bandgap of amorphous silicon. Capacitance-voltage and current-voltage measurements on these devices present strong evidence for the existence of the buried-channel. We achieve a record field effect mobility in saturation of 1.68 cm² /V-s with amorphous silicon deposited at 230°C, and an acceptable mobility of 0.44 cm²/V-s with amorphous silicon deposited at 125°C     

A novel self-aligned polycrystalline silicon thin-film transistorusing silicide layers

A novel self-aligned polycrystalline silicon (poly-Si) thin-film transistor (TFT) was fabricated using the three layers of poly-Si, silicon-nitride, and thin amorphous silicon. Gate and source/drain silicide formation was carried out simultaneously following silicon nitride and amorphous silicon patterning, enabling the use of only two mask steps for the TFT. The fabricated poly-Si TFT using laser annealed poly-Si exhibited a field-effect mobility of 30.6 cm²/Vs, threshold voltage of 0.5 V, subthreshold slope of 1.9 V/dec., on/off current ratio of ~10⁶, and off-state leakage current of 7.88×10^-12 A/μm at the drain voltage of 5 V and gate voltage of -10 V     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

A high performance thin-film transistor using a low temperaturepoly-Si by silicide mediated crystallization

Electric field enhanced silicide mediated crystallization (SMC) was introduced for low-temperature polycrystalline silicon thin-film transistors (TFTs) on glass substrates. The amorphous silicon (a-Si) film having an average Ni thickness of 0.15 Å, was completely crystallized at a temperature of 480°C within 30 min in the presence of an electric field of 40 V/cm. The poly-Si is composed of needlelike crystallites with a few μm length and about 50 nm width. The poly-Si TFT using the SMC exhibited a field effect mobility of 86 cm²/Vs, a threshold voltage of -0.6 V, and a subthreshold slope of 0.6 V/dec     

A new polycrystalline silicon TFT with a single grain boundary inthe channel

A new excimer laser annealing method, which results in large lateral polysilicon grains exceeding 1.5 μm, has been proposed and polycrystalline silicon thin film transistors (poly-Si TFTs) with a single grain boundary in the channel have been successfully fabricated. The proposed method employs a lateral grain growth phenomenon obtained by excimer laser irradiation on an amorphous silicon layer with pre-patterned aluminum film. The aluminum patterns act as a masking layer of the incident laser beam for the selective melting of the amorphous silicon layer. Uniform and large grains are obtained near the edge of the aluminum patterns. When two aluminum patterns are separated by a 2 μm space, the solidified region (i.e., poly-Si channel) exhibits a single grain boundary. The n-channel poly-Si TPT fabricated by the proposed method shows considerably improved I-V characteristics, such as high field effect mobility exceeding 240 cm²/Vs     

Hydrogenated amorphous silicon thin film transistor fabricated onplasma treated silicon nitride

We have demonstrated that the performance of the inverted staggered, hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) is improved by a He, H₂, NH₃ or N₂ plasma treatment for a short time on the surface of silicon nitride (SiN _x) before a-Si:H deposition. With increasing plasma exposure time, the field-effect mobility increase at first and then decrease, but the threshold voltage changes little. The a-Si:H TFT with a 6-min N₂ plasma treatment on SiN_x exhibited a field effect mobility of 1.37 cm²/Vs, a threshold voltage of 4.2 V and a subthreshold slope of 0.34 V/dec. It is found that surface roughness of SiN_x is decreased and N concentration in the SiN _x at the surface region decreases using the plasma treatment     

Self-aligned gate and source drain contacts in inverted-staggereda-Si:H thin-film transistors fabricated using selective area siliconPECVD

This article demonstrates full self-aligned inverted-staggered amorphous silicon thin-film transistors (TFT's) fabricated using selective plasma deposition of doped microcrystalline silicon source/drain contacts. Back-side exposure, using the bottom metal gate as the mask, produced the self-aligned contact openings. Selective deposition of the n+ silicon contact layer assures self-aligned ion resistance contacts and eliminates the need for reactive ion etching of the n+ silicon. Complete TFT fabrication requires no critical alignment steps. Transistors have linear mobility between 0.6 and 1.1 cm² /Vs, threshold voltage of 3.0 V, and sub-threshold slope of 0.35 V/decade. The OFF current is <10^-11 A with -10 V gate voltage and 10 V between the source and drain, and ON/OFF ratios exceed 10     

Low temperature polycrystalline silicon thin film transistor withsilicon nitride ion stopper

The authors have fabricated a new low temperature polycrystalline silicon (poly-Si) thin film transistor (TFT) with silicon nitride (SiN _x) ion-stopper and laser annealed poly-Si. The fabricated poly-Si TFT using SiN_x as the ion-stopper as well as the gate insulator exhibited a field effect mobility of 110 cm²/Vs, subthreshold voltage of 5.5 V, subthreshold slope of 0.48 V/dec., and on/off current ratio of ~10⁶. Low off-state leakage current of 2.4×10^-2 A/μm at the drain voltage of 5 V and the gate voltage of -5 V was achieved     

Amorphous silicon as a resist material

Lithographic properties of amorphous silicon films exposed to glow-discharge hydrogen plasma and ion beams have been investigated. The rate of film etching by a CF₄ plasma is lowered by exposure, giving rise to a negative resist behavior of the material. The sensitivity and contrast are ~10¹⁸ ions/cm² and 1.1, respectively. The effect of exposure time on etching characteristics was also studied     

Poly-Si/poly-SiCx heterojunction thin-film transistors

We have proposed heterojunction thin-film transistors having a stacked structure of poly-crystal silicon-carbon (SiC_x) and Si thin films, both of which are prepared by an excimer-laser crystallization method. A Si/SiC_x interface after intense excimer-laser irradiation for crystallization, was as abrupt as that of the as-deposited and amorphous structure. The device had a relatively high mobility of about 4 cm²/Vs and a sufficiently low leakage current of an order of 10^-14 A/μm even under intense light illumination conditions     

High-performance thin-film transistors in low-temperature crystallized LPCVD amorphous silicon films

Thin-film transistors (TFT's) were fabricated in low-temperature (550°C) crystallized amorphous LPCVD silicon films. The performance of these devices was found to depend upon the deposition temperature. Low threshold voltages and effective mobilities as high as 32 cm²/V.s are reported for devices fabricated in 150-nm-thick films with maximum processing temperature of 860°C. The performance of these devices is shown to be far superior to devices fabricated in as-deposited polycrystalline silicon films.     

Amorphous-silicon thin-film transistor with liquid phase depositionof silicon dioxide gate insulator

The liquid phase deposition of silicon dioxide (LPD-SiO₂) at 50°C has been successfully applied as the gate insulator for inverted, staggered amorphous silicon thin-film transistors (TFTs). The maximum field-effect mobility of the TFTs, estimated from the saturation region, was 0.53 cm²/V-s, comparable to that obtained for conventional, silicon nitride (SiN_x ) gate transistors. The threshold voltage and subthreshold swing were 6.2 V and 0.76 V/decade, respectively. Interface and bulk characteristics are as good as those obtained for silicon nitride (SiN _x) films deposited by plasma enhanced chemical vapor deposition     

A study of frequency response in silicon heterojunction bipolartransistors with amorphous silicon emitters

A detailed physical model of amorphous silicon (a-Si:H) is incorporated into a two-dimensional device simulator to examine the frequency response limits of silicon heterojunction bipolar transistors (HBT's) with a-Si:H emitters. The cutoff frequency is severely limited by the transit time in the emitter space charge region, due to the low electron drift mobility in a-Si:H, to 98 MHz which compares poorly with the 37 GHz obtained for a silicon homojunction bipolar transistor with the same device structure. The effects of the amorphous heteroemitter material parameters (doping, electron drift mobility, defect density and interface state density) on frequency response are then examined to find the requirements for an amorphous heteroemitter material such that the HBT has better frequency response than the equivalent homojunction bipolar transistor, We find that an electron drift mobility of at least 100 cm² V^-1 s^-1 is required in the amorphous heteroemitter and at a heteroemitter drift mobility of 350 cm ² V^-1 s^-1 and heteroemitter doping of 5×10¹⁷ cm^-3, a maximum cutoff frequency of 52 GHz can be expected     

An amorphous silicon thin-film transistor with fully self-alignedtop gate structure

We have developed a novel fully self-aligned top gate amorphous silicon thin-film transistor, which shows excellent transistor characteristics. Self-alignment is achieved by patterning the gate electrode and then etching the silicon nitride gate insulator, followed by silicidation and ion implantation of the exposed a-Si in the contact regions. We obtain a long channel saturated mobility of 0.9 cm² V^-1 s^-1, while for channel lengths of 6 μm, we obtain an effective mobility of 0.6 cm² V^-1 s^-1, in the saturated region and 0.5 cm² V ^-1 s^-1, in the linear region. This high level of performance, together with the negligible parasitic capacitance of the self-aligned structure, makes this transistor suitable for new demanding applications in active matrix liquid crystal displays and large area X-ray image sensors     

A polycrystalline silicon thin-film transistor with a thinamorphous buffer

We have developed a novel, low off-state leakage current polycrystalline silicon (poly-Si) thin-film transistor (TFT) by introducing a very thin hydrogenated amorphous silicon (a-Si:H) buffer on the poly-Si active layer. The a-Si:H buffer is formed on the whole poly-Si and thus no additional mask step is needed. With an a-Si:H buffer on poly-Si, the off-state leakage current of a coplanar TFT is remarkably reduced, while the reduction of the on-state current is relatively small. The poly-Si TFT with an a-Si:H buffer exhibited a field effect mobility of 12 cm²/Vs and an off-state leakage current of 3 fA/μm at the drain voltage of 1 V and the gate voltage of -5 V     

A novel coplanar amorphous silicon thin-film transistor usingsilicide layers

A novel, coplanar, hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) was fabricated by depositing a triple layer consisting of a-Si:H, silicon-nitride, and a-Si:H. After patterning the top two layers in the gate stack, the devices were doped and a 30 nm Ni layer was deposited. The devices were then annealed for 1 h at 230°C to form self-aligned, low resistive Ni-silicide. The fabricated coplanar a-Si:H TFT exhibits a field effect mobility of 0.6 cm²/Vs, a threshold voltage of 2 V, a subthreshold slope of 0.4 V/dec, and an on/off current ratio of ~10⁷