共查询到20条相似文献,搜索用时 31 毫秒
1.
《Distributed Systems Online, IEEE》2008,9(8):1-1
Parallel computing is rapidly entering mainstream computing, and multicore processors can now be found in the heart of supercomputers, desktop computers, and laptops. Consequently, applications will increasingly need to be parallelized to fully exploit the multicore processor throughput gains that are becoming available. Unfortunately, writing parallel code is more complex than writing serial code. An introductory parallel computing course aims to introduce students to this technology shift and to explain that parallelism calls for a different way of thinking and new programming skills. The course covers theoretical topics and offers practical experience in writing parallel algorithms on state-of-the-art parallel computers, parallel programming environments, and tools. 相似文献
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多核处理器已经成为当前处理器设计的主流,其并行处理能力显著提高了处理器的性能,同时,多核处理器本身的高度集成度也使其功耗显著上升,从而在一定程度上限制了多核处理器的发展。本文描述了低功耗设计的基本理论、常用的低功耗设计技术和多核处理器中的功耗评估技术,并分析和总结了低功耗多核处理器研究的最新进展,可为多核处理器的设计提供有益的参考。 相似文献
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Based on its simplicity and user-friendly characteristics, OpenMP has become the standard model for programming on shared-memory architectures. Checkpointing-aided parallel execution (CAPE) is an approach that utilizes the discontinuous incremental checkpointing technique (DICKPT) to translate and execute OpenMP programs on distributed-memory architectures automatically. Currently, CAPE implements the OpenMP execution model by utilizing the DICKPT to distribute parallel jobs and their data to slave machines, and then collects the results after executing these distributed jobs. Although this model has been proven to be effective in terms of performance and compatibility with OpenMP on distributed-memory systems, it cannot fully exploit the capabilities of multicore processors. This paper presents a novel execution model for CAPE that utilizes two levels of parallelism. In the proposed model, we add another level of parallelism in the form of multithreaded processes on slave machines with the goal of better exploiting their multicore CPUs. Initial experimental results presented near the end of this paper demonstrate that this model provides significantly enhanced CAPE performance. 相似文献
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Because of the intrinsic lack of internal‐system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on‐chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run‐stop‐type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG‐based scanning operation. We apply this on‐chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach. 相似文献
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Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low‐power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low‐power commutators based on an advanced interconnection, and parallel‐pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel‐pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures. 相似文献
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General-purpose multicore processors are being accepted in all segments of the industry, including signal processing and embedded space, as the need for more performance and general-purpose programmability has grown. Parallel processing increases performance by adding more parallel resources while maintaining manageable power characteristics. The implementations of multicore processors are numerous and diverse. Designs range from conventional multiprocessor machines to designs that consist of a "sea" of programmable arithmetic logic units (ALUs). In this article, we cover some of the attributes common to all multicore processor implementations and illustrate these attributes with current and future commercial multicore designs. The characteristics we focus on are application domain, power/performance, processing elements, memory system, and accelerators/integrated peripherals. 相似文献
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Shikano H. Ito M. Onouchi M. Todaka T. Tsunoda T. Kodama T. Uchiyama K. Odaka T. Kamei T. Nagahama E. Kusaoke M. Nitta Y. Wada Y. Kimura K. Kasahara H. 《Solid-State Circuits, IEEE Journal of》2008,43(4):902-910
This paper describes a heterogeneous multi-core processor (HMCP) architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-core having homogeneous processor cores and dynamically reconfigurable processor (DRP) ACC cores in a preliminary evaluation of the HMCP architecture. The performance evaluation revealed that 54times AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1- 2 min. 相似文献
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针对多核环境中高速无线信号的加扰、解扰,提出了一种基于稀疏矩阵的多核并行扰码方法。首先对输入信号进行串/并转换,并将各路信号分别送入对应的处理器核;考虑基于稀疏矩阵的并行扰码生成器,在单个处理器核内,将其生成的伪随机码与输入信号进行模二加运算,得到单路信号的扰码输出;最后将多路并行的扰码输出变换为串行输出。运算量分析结果表明,采用IEEE 802.11n中的扰码生成多项式,与普通矩阵乘法实现的多核并行扰码方法相比,基于稀疏矩阵的多核并行扰码方法,其运算量降低了一个数量级。 相似文献
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《IEEE instrumentation & measurement magazine》2009,12(4):26-29
This paper examined how recent innovations in processor technology are pushing the limits for ATE applications. Various multicore programming techniques were discussed including task parallelism, data parallelism, and pipelining. In addition, an example of optimizing complex analysis was covered. The benefits of adopting multicore technology and parallel software architectures include a reduction in overall test time, more sophisticated simulation approaches, and the ability to analyze complex systems. 相似文献
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《International Journal of Electronics》2013,100(10):1754-1764
This article proposes design and architecture of a dynamically scalable dual-core pipelined processor. Methodology of the design is the core fusion of two processors where two independent cores can dynamically morph into a larger processing unit, or they can be used as distinct processing elements to achieve high sequential performance and high parallel performance. Processor provides two execution modes. Mode1 is multiprogramming mode for execution of streams of instruction of lower data width, i.e., each core can perform 16-bit operations individually. Performance is improved in this mode due to the parallel execution of instructions in both the cores at the cost of area. In mode2, both the processing cores are coupled and behave like single, high data width processing unit, i.e., can perform 32-bit operation. Additional core-to-core communication is needed to realise this mode. The mode can switch dynamically; therefore, this processor can provide multifunction with single design. Design and verification of processor has been done successfully using Verilog on Xilinx 14.1 platform. The processor is verified in both simulation and synthesis with the help of test programs. This design aimed to be implemented on Xilinx Spartan 3E XC3S500E FPGA. 相似文献
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Ardavan Pedram John D. McCalpin Andreas Gerstlauer 《Journal of Signal Processing Systems》2014,77(1-2):169-190
FFT algorithms have memory access patterns that prevent many architectures from achieving high computational utilization, particularly when parallel processing is required to achieve the desired levels of performance. Starting with a highly efficient hybrid linear algebra/FFT core, we co-design the on-chip memory hierarchy, on-chip interconnect, and FFT algorithms for a multicore FFT processor. We show that it is possible to to achieve excellent parallel scaling while maintaining power and area efficiency comparable to that of the single-core solution. The result is an architecture that can effectively use up to 16 hybrid cores for transform sizes that can be contained in on-chip SRAM. When configured with 12MiB of on-chip SRAM, our technology evaluation shows that the proposed 16-core FFT accelerator should sustain 388 GFLOPS of nominal double-precision performance, with power and area efficiencies of 30 GFLOPS/W and 2.66 GFLOPS/mm2, respectively. 相似文献
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Local processing, which is a dominant type of processing in image and video applications, requires a huge computational power
to be performed in real-time. However, processing locality, in space and/or in time, allows to exploit data parallelism and
data reusing. Although it is possible to exploit these properties to achieve high performance image and video processing in
multi-core processors, it is necessary to develop suitable models and parallel algorithms, in particular for non-shared memory
architectures. This paper proposes an efficient and simple model for local image and video processing on non-shared memory
multi-core architectures. This model adopts a single program multiple data approach, where data is distributed, processed
and reused in an optimal way, regarding the data size, the number of cores and the local memory capacity. The model was experimentally
evaluated by developing video local processing algorithms and programming the Cell Broadband Engine multi-core processor,
namely for advanced video motion estimation and in-loop deblocking filtering. Furthermore, based on these experiences it is
also addressed the main challenges of vectorization, and the reduction of branch mispredictions and computational load imbalances.
The limits and advantages of the regular and adaptive algorithms are also discussed. Experimental results show the adequacy
of the proposed model to perform local video processing, and that real-time is achieved even to process the most demanding
parts of advanced video coding. Full-pixel motion estimation is performed over high resolution video (720×576 pixels) at a
rate of 30 frames per second, by considering large search areas and five reference frames. 相似文献
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In this paper, we demonstrate the use of finite-dimension linear programming to maximize the number of partial good multicore processor chips in a symmetric multiprocessing (SMP) node of a given logical size and physical footprint. It is asserted that to the first order the cost of a productized processor chip will be proportional to the scrap of a processor chip containing good cores but being unusable for the implementation of an SMP node. Therefore, the tradeoff between the number of processing units (PUs) on a chip and the total number of PUs on an SMP node is examined. This paper shows that an optimized SMP offering can be found so that the total chip cost of a high-end system can be minimized. However, such cost reduction will limit the SMP node size for a given processor chip yield. It will also be shown that as the chip yield improves the SMP node size that can be profitably implemented will increase. 相似文献
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In many scientific and signal processing applications, there are increasing demands for large-volume and/or high-speed computations which call for not only high-speed computing hardware, but also for novel approaches in computer architecture and software techniques in future supercomputers. Tremendous progress has been made on several promising parallel architectures for scientific computations, including a variety of digital filters, fast Fourier transform (FFT) processors, data-flow processors, systolic arrays, and wavefront arrays. This paper describes these computing networks in terms of signal-flow graphs (SFG) or data-flow graphs (DFG), and proposes a methodology of converting SFG computing networks into synchronous systolic arrays or data-driven wavefront arrays. Both one- and two-dimensional arrays are discussed theoretically, as well as with illustrative examples. A wavefront-oriented programming language, which describes the (parallel) data flow in systolic/wavefront-type arrays, is presented. The structural property of parallel recursive algorithms points to the feasibility of a Hierarchical Iterative Flow-Graph Design (HIFD) of VLSI Array Processors. The proposed array processor architectures, we believe, will have significant impact on the development of future supercomputers. 相似文献
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Murali S. Atienza D. Meloni P. Carta S. Benini L. De Micheli G. Raffo L. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(8):869-880
Today, chip multiprocessors (CMPs) that accommodate multiple processor cores on the same chip have become a reality. As the communication complexity of such multicore systems is rapidly increasing, designing an interconnect architecture with predictable behavior is essential for proper system operation. In CMPs, general-purpose processor cores are used to run software tasks of different applications and the communication between the cores cannot be precharacterized. Designing an efficient network-on-chip (NoC)-based interconnect with predictable performance is thus a challenging task. In this paper, we address the important design issue of synthesizing the most power efficient NoC interconnect for CMPs, providing guaranteed optimum throughput and predictable performance for any application to be executed on the CMP. In our synthesis approach, we use accurate delay and power models for the network components (switches and links) that are obtained from layouts of the components using industry standard tools. The synthesis approach utilizes the floorplan knowledge of the NoC to detect timing violations on the NoC links early in the design cycle. This leads to a faster design cycle and quicker design convergence across the high-level synthesis approach and the physical implementation of the design. We validate the design flow predictability of our proposed approach by performing a layout of the NoC synthesized for a 25-core CMP. Our approach maintains the regular and predictable structure of the NoC and is applicable in practice to existing NoC architectures. 相似文献
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Senyo Apewokin Brian Valentine Jee Choi Linda Wills Scott Wills 《Journal of Signal Processing Systems》2011,62(1):65-76
Current trends in microprocessor design integrate several autonomous processing cores onto the same die. These multicore architectures
are particularly well-suited for computer vision applications, where it is typical to perform the same set of operations repeatedly
over large datasets. These memory- and computation-intensive applications can reap tremendous performance and accuracy benefits
from concurrent execution on multi-core processors. However, cost-sensitive embedded platforms place real-time performance
and efficiency demands on techniques to accomplish this task. Furthermore, parallelization and partitioning techniques that
allow the application to fully leverage the processing capabilities of each computing core are required for multi-core embedded
vision systems. In this paper, we evaluate background modeling techniques on a multicore embedded platform, since this process
dominates the execution and storage costs of common video analysis workloads. We introduce a new adaptive backgrounding technique,
multimodal mean, which balances accuracy, performance, and efficiency to meet embedded system requirements. Our evaluation
compares several pixel-level background modeling techniques in terms of their computation and storage requirements, and functional
accuracy for three representative video sequences, across a range of processing and parallelization configurations. We show
that the multimodal mean algorithm delivers comparable accuracy of the best alternative (Mixture of Gaussians) with a 3.4×
improvement in execution time and a 50% reduction in required storage for optimal block processing on each core. In our analysis
of several processing and parallelization configurations, we show how this algorithm can be optimized for embedded multicore
performance, resulting in a 25% performance improvement over the baseline processing method. 相似文献