利用金属过渡层低温键合硅晶片

在Si/Si之间采用Ti/Au金属过渡层,实现了Si/Si低温键合,键合温度可低至414 ℃.采用拉伸强度测试对Si/Si键合结构的界面特性进行测试,结果表明,键合强度高于1.27MPa;I-V测试表明,Si/Ti/Au/Ti/Si键合界面基本为欧姆接触;X射线光电子能谱(XPS)测试结果进一步表明,界面主要为Si-Au共晶合金.不同温度的变温退火实验表明,键合温度越高,键合强度越大,且渐变退火有利于提高键合强度.     

利用金属过渡层低温键合硅晶片

在Si/Si之间采用Ti/Au金属过渡层,实现了Si/Si低温键合,键合温度可低至414 ℃.采用拉伸强度测试对Si/Si键合结构的界面特性进行测试,结果表明,键合强度高于1.27MPa;I-V测试表明,Si/Ti/Au/Ti/Si键合界面基本为欧姆接触;X射线光电子能谱(XPS)测试结果进一步表明,界面主要为Si-Au共晶合金.不同温度的变温退火实验表明,键合温度越高,键合强度越大,且渐变退火有利于提高键合强度.     

压阻加速度计的Au-Si共晶键合

通过将压阻加速度计上帽与结构片的键合 ( 36 5℃保温 10min) ,再进行下帽与结构片的键合 ( 380± 10℃保温2 0min) ,成功进行了三层键合 .测得的键合强度约为 2 30MPa.硅片 基体 /SiO2 /Cr/Au层和硅片之间键合时 ,SiO2 溶解而形成CrSi2 硅化物 .共晶反应因Cr层而被推迟 ,键合温度高出共晶温度 2 0℃左右 ,从而避免了由于Au元素向硅中扩入而造成的污染 ,进而避免可能造成的对集成微电子器件性能的影响 .试验还证明硅基体 SiO2 /Cr/Au/Poly Si/Au键合层结构设计模型也遵循这一键合过程中的原子扩散理论.     

一种Au-Si键合强度检测结构与试验

设计了一种Au Si键合强度检测结构。通过对一组不同尺寸压臂式测试结构的检测 ,可以由结构尺寸半定量地折算出键合面的键合强度 ;采用同一结构尺寸 ,可以比较不同条件下键合强度的相对大小 ;此结构还可用于其它类型键合强度的比较和测试。通过压臂法检测了Au Si键合强度 ,其数值高于硅片基体本身的强度     

含TSV结构的3D封装多层堆叠Cu/Sn键合技术

研究了利用Cu/Sn对含硅通孔(TSV)结构的多层芯片堆叠键合技术。采用刻蚀和电镀等工艺,制备出含TSV结构的待键合芯片,采用扫描电子显微镜(SEM)对TSV形貌和填充效果进行了分析。研究了Cu/Sn低温键合机理,对其工艺进行了优化,得到键合温度280℃、键合时间30 s、退火温度260℃和退火时间10 min的最佳工艺条件。最后重点分析了多层堆叠Cu/Sn键合技术,采用能谱仪(EDS)分析确定键合层中Cu和Sn的原子数比例。研究了Cu层和Sn层厚度对堆叠键合过程的影响,获得了10层芯片堆叠键合样品。采用拉力测试仪和四探针法分别测试了键合样品的力学和电学性能,同时进行了高温测试和高温高湿测试,结果表明键合质量满足含TSV结构的三维封装要求。     

AlGaInP/Si的键合研究

金锡(AuSn)合金作为粘合介质,实现了AlGaInP/Si的异质键合.在室温下键合样品的I-V特性表明AuSn合金对载流子通过界面未见不良影响,截面的显微照片表明键合质量良好.反射谱测试表明键合合金层可以作为反射器,这一特征是AlGaInP发光器件与Si集成的有利条件.     

AlGaInP/Si的键合研究

金锡(AuSn)合金作为粘合介质,实现了AlGaInP/Si的异质键合.在室温下键合样品的I-V特性表明AuSn合金对载流子通过界面未见不良影响,截面的显微照片表明键合质量良好.反射谱测试表明键合合金层可以作为反射器,这一特征是AlGaInP发光器件与Si集成的有利条件.     

压阻加速度计的Au-Si共晶键合

通过将压阻加速度计上帽与结构片的键合(365℃保温10min),再进行下帽与结构片的键合(380±10℃保温20min),成功进行了三层键合.测得的键合强度约为230MPa.硅片-基体/SiO2/Cr/Au层和硅片之间键合时,SiO2溶解而形成CrSi2硅化物.共晶反应因Cr层而被推迟,键合温度高出共晶温度20℃左右,从而避免了由于Au元素向硅中扩入而造成的污染,进而避免可能造成的对集成微电子器件性能的影响.试验还证明硅基体-SiO2/Cr/Au/Poly-Si/Au键合层结构设计模型也遵循这一键合过程中的原子扩散理论.     

GaN外延材料测试技术的研究

分别用金属In和Ti/Al/Ni/Au合金层制备GaN HEMT结构外延片的霍尔测试电极,并对样品进行霍尔测试.发现In金属与外延片形成非欧姆接触,Ti/Al/Ni/Au合金层与外延片形成良好的欧姆接触.用电化学C-V方法测试样品,得到的载流子浓度与合金电极制备的样品经霍尔测试得到的载流子浓度一致,从而验证了此种霍尔测试方法的准确性,为GaN外延材料的测试提出了准确可行的测试方法.     

基于Au/Au直接键合的高亮度ODRLED

提出利用Au/Au直接键合制作高亮度全方位反光镜(ODR)LED的新工艺。工艺采用Si做转移衬底,氧化铟锡(ITO)做窗口层和缓冲层,在0.35mPa压力,260°C的低温下实现Au/Au固相直接键合。直接键合后,Al-GaInP有源区与Si衬底结合牢固完整,保证了全方位反光镜的性能。在正向电流20mA下,键合ODR结构LED的正向压降是常规吸收衬底LED的80%,光输出功率和流明效率是常规吸收衬底LED的1.5倍和2.1倍。     

界面热应力对InP/Si键合质量的影响

通过实验和理论计算,分析了InP/Si键合过程中,界面热应力的分布情况、影响键合结果的关键应力因素及退火温度的允许范围。分析结果表明,由剪切应力和晶片弯矩决定的界面正应力是晶片中心区域大面积键合失败的主要原因,为保证良好的键合质量,InP/Si键合退火温度应该在300～350℃范围内选取。具体实验验证表明,该理论计算值与实验结果相一致。最后,在300℃退火条件下,很好地实现了2inInP/Si晶片键合,红外图像显示,界面几乎没有空洞和裂隙存在,有效键合面积超过90%。     

Nanoadhesion layer for enhanced Si–Si and Si–SiN wafer bonding

Direct wafer bonding of Si–Si and Si–SiN wafers was demonstrated using a nanoadhesion layer at room temperature. The two mating surfaces were cleaned by an Ar-ion beam and simultaneously deposited with ultrathin Fe layers (known as nanoadhesion layers). The ultrathin Fe layers imparted high bond strengths to Si–Si and Si–SiN bonds without heat treatment. Transmission electron microscopy revealed that the Si–Si and Si–SiN interfaces were tightly bonded and defect free. Moreover, the formation of crystalline iron silicide across the interface was found to enhance Si–Si wafer bonding. In addition to FeSi, an amorphous layer formed at the Si–SiN interface, resulting in a high bond strength at room temperature.     

Fluxless Wafer Bonding in Vacuum Using Electroplated Sn–Ag Layers

A wafer-to-wafer bonding process using Sn-Ag solder without any flux is successfully developed. This fluxless or flux-free feature makes void-free and uniform bonding layers possible. This is in contrast to the fluxing process employed in nearly all soldering processes adapted in the electronic industry. With the use of flux, the flux or flux residues are easily trapped in the solder joint, resulting in voids and uneven solder layers. This is particularly true if the bonding area is large, such as the entire wafer. Thus, void-free wafer bonding using solders has never been reported. It is thus clear that the key to achieve void-free wafer soldering is to eliminate flux completely. The new fluxless process is performed in a vacuum furnace built in house to inhibit solder oxidation. To prevent oxidation during solder manufacturing, a thin Ag capping layer is plated over the Sn layer right after the Sn layer is plated over an entire 2-in silicon wafer having Cr/Au under bump metallurgy (UBM). This outer Ag layer is critical in preventing the inner Sn layer from oxidation when the wafer is exposed to air. The Si wafer with Cr/Au/Sn/Ag structure is bonded with another Si wafer with Cr/Au at 240degC in the vacuum furnace. To evaluate the joint quality and study the microstructure and composition, scanning acoustic microscopy (SAM), scanning electron microscopy (SEM), and energy dispersive X-ray spectroscopy (EDX) are used. A solder joint with only 1% void area is accomplished. The initial success of this process illustrates that it is indeed possible to bond entire wafers together with a thin metallic joint of high quality. This fluxless bonding technique can be extended to bonding wafers of different materials for new device and packaging applications.     

基于硼酸溶液处理的GaAs/InP低温晶片键合技术

提出了一种基于硼酸溶液的GaAs/InP低温晶片键合技术,实现了GaAs/InP基材料间简单、无毒性的高质量、低温(290℃)晶片键合。GaAs/InP键合晶片解理截面的扫描电子显微镜(SEM)图显示,键合界面整齐,没有裂缝和气泡。通过键合过程,InP上的In0.53Ga0.47As/InP多量子阱结构转移到了GaAs基底上。X射线衍射及荧光谱显示,键合后的多量子阱晶体质量未变。二次离子质谱(SIMS)和Raman光谱图显示,GaAs/InP键合晶片的中间层厚度约为17 nm,界面处B元素有较高的浓度,键合晶片的中间层很薄,因此可以得到较好的电学、光学特性。     

Thermal stability of back side metallization multilayer for power device application

Metallization multilayers on the back side of a power device were focused in this study. Si wafers coated with high melting point metals were exposed at 300 °C for 300 h to investigate diffusion condition of the metallization layer. We developed and examined the thermal stability of die bonding material (Au paste) including sub–micrometer–sized Au particles. Auger electron spectroscopy was applied to observe the atomic composition of the multilayers in depth direction after the high temperature aging. Surface morphology was observed using optical microscope and scanning electron microscope. While atomic composition on Ti/Au changed drastically after the high temperature aging, other multilayers maintained their metallization composition. However, the surface morphology was slightly changed on Ti/Ru/Au, W/Au, and Ta/Au. Bond strength on the Ti/Pt/Au kept over 40 MPa with unified bonding layer after exposing at 300 °C for 1000 h.     

一种基于Ag-Sn等温凝固的圆片键合技术

研究了用Ag-Sn作为键合中间层的圆片健合。相对于成熟的Au-Sn键合系统(典型键合温度是280℃),该系统可以提供更低成本、更高键合后分离(De-Bonding)温度的圆片级键合方案。使用直径为100mm硅片,盖板硅片上溅射多层金属Ti/Ni/Sn/Au,利用Lift-off工艺来形成图形。基板硅片上溅射Ti/Ni/Au/Ag。硅片制备好后,将盖板和基板叠放在一起送入键合机进行键合。键合过程在N2气氛中进行,键合过程中不需要使用助焊剂。研究了不同键合参数,如键合压力、温度等对键合结果的影响。剪切强度测试表明样品的剪切强度平均在55.17MPa。TMA测试表明键合后分离温度可以控制在500℃左右。He泄漏测试证明封接的气密性极好。     

Wafer Direct Bonding: From Advanced Substrate Engineering to Future Applications in Micro/Nanoelectronics

Wafer direct bonding refers to the process of adhesion of two flat mirror-polished wafers without using any intermediate gluing layers in ambient air or vacuum at room temperature. The adhesion of the two wafers occurs due to attractive long range van der Waals or hydrogen bonding forces. At room temperature the bonding energy of the interface is low and higher temperature annealing of the bonded wafer pairs has to be carried out to enhance the bonding energy. In this paper, we describe the prerequisites for the wafer-bonding process to occur and the methods to prepare the suitable surfaces for wafer bonding. The characterization techniques to assess the quality of the bonded interfaces and to measure the bonding energy are presented. Next, the applications of wafer direct bonding in the fabrication of novel engineered substrates such as "silicon-on-insulator" and other "on-insulator" substrates are detailed. These novel substrates, often called hybrid substrates, are fabricated using wafer bonding and layer splitting via a high dose hydrogen/helium implantation and subsequent annealing. The specifics of this process, also known as the smart-cut process, are introduced. Finally, the role of wafer bonding in future nanotechnology applications such as nanotransistor fabrication, three-dimensional integration for high-performance micro/nanoelectronics, nanotemplates based on twist bonding, and nano-electro-mechanical systems is discussed     

SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层.为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数.制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数.实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012 cm-2·eV-1@0.2 eV,SiC MOSFET沟道载流子迁移率达到17 cm2·V-1·s-1.     

Transfer of GaN-Based Light-Emitting Diodes From Silicon Growth Substrate to Copper

III-nitride light-emitting diodes (LEDs) grown on Si (111) substrates have the potential of low-cost manufacturing for solid-state lighting and display, by taking advantage of the well-developed IC technologies of silicon. In this letter, LEDs grown on silicon substrates were transferred onto copper substrates, to maximize light extraction and heat dissipation. On Si substrates, $hbox{300} times hbox{300} muhbox{m}^{2}$ multiple quantum well InGaN LEDs were first grown and processed. The top surface of the fabricated devices was then temporarily bonded to a sapphire wafer and the Si substrate was chemically etched. Ti/Al/Ti/Au layers were deposited on the backside of LEDs. An 80-$muhbox{m}$ -thick copper layer was electroplated and the temporary bonding was removed, resulting in LEDs on copper substrate. The optical output power of LEDs on copper increased by $sim$ 70% as compared to that of the LEDs on silicon. The improved performance was attributed to the removal of the light-absorbing Si substrate and the good thermal conductivity of copper.