共查询到17条相似文献,搜索用时 187 毫秒
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介绍了一种基于可编程逻辑器件FPGA和硬件描述语言VHDL的32位ALU的设计方法。该ALU采取层次化设计方法,由控制模块、逻辑模块、加减法模块、乘法模块和除法模块组成,能实现32位有符号数和无符号数的加减乘除运算,另外还能实现9种逻辑运算、6种移位运算以及高低字节内容互换。该ALU在QuartusII软件环境下进行了功能仿真, 通过验证表明,所设计的ALU完全正确,可供直接调用。 相似文献
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算术逻辑部件(ALU)是整个微控制单元(MCU)运算的核心,相当于人类的大脑。ALU的运算性能直接影响整个MCU运行的效率。一般简易MCU的内核只需进行加、减、逻辑运算等,不涉及到乘除,针对此特点设计了一种简易的加法电路,并在FPGA下进行仿真验证,仿真结果达到了设计要求,该ALU部分能根据不同的使能信号实现加、减、逻辑与或非以及数据传输功能。 相似文献
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介绍了一种使用可编程逻辑器件FPGA和VHDL语言实现32位除法器的设计方法。该除法器不仅可以实现有符号数运算,也可以实现无符号数的运算。除法器采用节省FPGA逻辑资源的时序方式设计,主要由移位、比较和减法三种操作构成。由于优化了程序结构,因此程序浅显易懂,算法简单,不需要分层次分模块进行。并使用Altera公司的QuartusⅡ软件对该除法器进行编译、仿真,得到了完全正确的结果。 相似文献
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与传统的FPGA相比,采用自适应逻辑模块架构的新一代高端FPGA StratixⅡ在完成通用算术和加法树功能上具有占用资源少、工作频率高、设计灵活等优点。加法运算是最基本的算术运算,是构成数字信号处理系统的基础。根据加法树设计原理,结合相关研究的新进展,提出了一种基于StratixⅡ的加法树解决方案,说明了其实现要点及其在高速数字相关器中的应用。 相似文献
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高速公路宏观动态模型研究对高速公路交通流的控制具有重要意义。以工控机为处理核心的系统存在的体积大、功耗大,不适宜长期在实际路口工作的缺陷,本文旨在研究一种基于FPGA的仿真实现高速公路宏观动态模型,以克服工控机的不足之处。设计了16位自定义浮点数,与Quartus II软件中公开浮点数运算IP核相比,能够在保证计算精度的前提下节省FPGA的逻辑资源。基于上述浮点数运算模块,本文对高速公路宏观动态交通流模型进行了FPGA的仿真实现,并将其结果与MATLAB运算结果进行对比。结果表明基于FPGA的仿真不仅能够满足仿真精度的指标,还可以获得更快的运算速度。 相似文献
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基于FPGA的算术逻辑单元设计 总被引:1,自引:0,他引:1
介绍了一种使用可编程逻辑器件FPGA和VHDL语言进行ALU设计的方法。并在加法器模块的设计中使用了超前进位的方法。使得所设计的ALU具有很好的稳定性和较高的速度。 相似文献
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采取基-4按频率抽取FFT算法,设计一种可在FPGA上实现的64点、32位长、定点复数FFT处理器.基-4堞形运算单元中采用六级流水线设计,并行处理4路输入/输出数据,能极大地提高FFT的处理速度.该设计采用VHDL描述的多个功能模块,经ModelSim对系统进行逻辑综合与时序仿真.实验证明,利用FPGA实现64点FFT,运算速度快,完全可以处理高速实时信号. 相似文献
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Arithmetic Logic Unit(ALU) as one of the main parts of any computing hardware plays an important role in digital computers. In quantum computers which can be realized by reversible logics and circuits, reversible ALUs should be designed. In this paper, we proposed three different designs for reversible 1-bit ALUs using our proposed 3×3 and 4×4 reversible gates called MEB3 and MEB4(Moallem Ehsanpour Bolhasani) gates, respectively. The first proposed reversible ALU consists of six logical operations. The second proposed ALU consists of eight operations, two arithmetic, and six logical operations. And finally, the third proposed ALU consists of sixteen operations, four arithmetic operations, and twelve logical operations. Our proposed ALUs can be used to construct efficient quantum computers in nanotechnology, because the proposed designs are better than the existing designs in terms of quantum cost, constant input, reversible gates used, hardware complexity, and functions generated. 相似文献
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分析了FIR滤波器的结构特点和基本原理,基于Matlab用窗函数法对FIR滤波器进行设计,并在Sireulink中进行系统仿真。最后,在FPGA中实现并利用SignalTap Ⅱ逻辑分析器对设计进行测试验证,测试结果与仿真结果一致。 相似文献
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Mahdi Fazeli Seyed-Ghassem Miremadi Alireza Haghdoost 《Microelectronics Reliability》2011,51(12):2374-2387
This paper presents a low cost fault-tolerant technique so called OWHR (Operand Width Aware Hardware Reuse) to ALU design in embedded processors. The OWHR technique is motivated by two facts: (1) Many of the produced and consumed values are narrow-width values in the embedded processors, i.e. they have leading zeros or ones in their most significant bits. This indicates that only a fraction of the circuit is performing useful operations when a particular arithmetic or logic circuit in the ALU is operating on narrow-width values; (2) other circuits of the ALU are not used, when a particular arithmetic or logic circuit is being utilized to perform a specific operation in the ALU in the embedded processors. To exploit the first fact for fault tolerance purpose, the unused parts of a particular arithmetic or logic circuit can be used to provide redundant computations. The second fact also offers us assisting the other unused arithmetic circuits of the ALU to provide redundant computation while a particular arithmetic circuit is being used to perform a specific operation. In this paper, we have implemented a 32-bit ALU protected by the OWHR technique using VHDL and we have extracted the results of power and performance overheads using Synopsis Design and Power Compiler. To do this, we have profiled the input operands of the adder and multiplier units by running some programs of MiBench embedded suite benchmark on an ARM processor performance mode. We have then applied the profiled operands to the implemented ALU to extract the power and performance overheads. The simulation results show that the proposed technique is capable of correcting about 56% of errors in the adder circuit and about 88% of errors in multiplier circuit while having the ability of detecting 100% of errors in the both of the circuits. Beside its high level of reliability, it offers the benefits of low power, and area overheads. 相似文献