一款便携式移动应用的低成本超高频无源射频识别读写器收发机芯片设计

A low cost integrated transceiver for mobile UHF passive RFID reader applications is implemented in a 0.18μm CMOS process. The transceiver contains an OOK modulator and a power amplifier in the transmitter chain, an IQ direct-down converter, variable-gain amplifiers, channel-select filters and a 10-bit ADC in the receiver chain. The measured output PldB power of the transmitter is 17.6 dBm and the measured receiver sensitivity is -70 dBm. The on-chip integer N synthesizer achieves a frequency resolution of 200 kHz with a phase noise of -104 dBc/Hz at 100 kHz frequency offset and -120.83 dBc/Hz at 1 MHz frequency offset. The transmitter, the receiver and the frequency synthesizer consume 201.34, 25.3 and 54 mW, respectively. The chip has a die area of 4 × 2.5 mm^2 including pads.     

Design of a passive UHF RFID tag for the ISO18000-6C protocol

This paper presents a new fully integrated wide-range UHF passive RFID tag chip design that is compatible with the ISO18000-6C protocol.In order to reduce the die area,an ultra-low power CMOS voltage regulator without resistors and an area-efficient amplitude shift keying demodulator with a novel adaptive average generator are both adopted.A low power clock generator is designed to guarantee the accuracy of the clock under±4%. As the clock gating technology is employed to reduce the power consumption of the baseband processor,the total power consumption of the tag is about 14μW with a sensitivity of-9.5 dBm.The detection distance can reach about 5 m under 4 W effective isotropic radiated power.The whole tag is fabricated in TSMC 0.18μm CMOS technology and the chip size is 880×880μm~2.     

集成片上天线的低成本低功耗超高频射频识别标签

This paper presents an EPC Class 1 Generation 2 compatible tag with on-chip antenna implemented in the SMIC 0.18 μm standard CMOS process.The UHF tag chip includes an RF/analog front-end, a digital baseband, and a 640-bit EEPROM memory.The on-chip antenna is optimized based on a novel parasitic-aware model.The rectifier is optimized to achieve a power conversion efficiency up to 40% by applying a self-bias feedback and threshold compensation techniques.A good match between the tag circuits and the on-chip antenna is realized by adjusting the rectifier input impedance.Measurements show that the presented tag can achieve a communication range of 1 cm with 1 W reader output power using a 1 × 1 cm2 single-turn loop reader antenna.     

A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider

A 1.2 GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18μm CMOS technology.A distributed biased varactor LC voltage-controlled oscillator is employed to achieve low tuning sensitivity and optimized phase noise performance.A high-speed and low-switching-noise divider-by-2 circuit based on a source-coupled logic structure is adopted to generate a quadrature(I/Q) local oscillating signal.A high-speed 8/9 dual-modulus prescaler(DMP),a programmable-delay phase frequency detector without dead-zone problem,and a programmable-current charge pump are also integrated into the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30 GHz,and the phase noise is-98.53 dBc/Hz at 100-kHz offset and -121.92 dBc/Hz at 1-MHz offset from the carrier frequency of 1.21 GHz. The power dissipation of the core circuits without the output buffer is 9.8 mW from a 1.8 V power supply.The total area of the receiver is 2.4×1.6 mm~2.     

Analysis and design of power efficient semi-passive RFID tag

The analysis and design of a semi-passive radio frequency identification(RFID) tag is presented.By studying the power transmission link of the backscatter RFID system and exploiting a power conversion efficiency model for a multi-stage AC-DC charge pump,the calculation method for semi-passive tag's read range is proposed.According to different read range limitation factors,an intuitive way to define the specifications of tag's power budget and backscatter modulation index is given.A test chip is implemen...     

一种用于RFID读写器的高集成CMOS功率放大器的设计与分析

To implement a fully-integrated on-chip CMOS power amplifier（PA） for RFID readers,the resonant frequency of each matching network is derived in detail.The highlight of the design is the adoption of a bonding wire as the output-stage inductor.Compared with the on-chip inductors in a CMOS process,the merit of the bondwire inductor is its high quality factor,leading to a higher output power and efficiency.The disadvantage of the bondwire inductor is that it is hard to control.A highly integrated class-E PA is implemented with 0.18-μm CMOS process.It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm.The maximum power-added efficiency（PAE） is 32.1%.Also,the spectral performance of the PA is analyzed for the specified RFID protocol.     

A novel power amplifier structure for RFID tag applications

A novel matching method between the power amplifier(PA) and antenna of an active or semi-active RFID tag is presented.A PCB dipole antenna is used as the resonance inductor of a differential power amplifier. The total PA chip area is reduced greatly to only 240×70μm~2 in a 0.18μm CMOS process due to saving two on-chip integrated inductors.Operating in class AB with a 1.8 V supply voltage and 2.45 GHz input signal,the PA shows a measured output power of 8 dBm at the 1 dB compression point.     

A △∑ fractional-N frequency synthesizer for FM tuner using low noise filter and quantization noise suppression technique

A △∑ fractional-N frequency synthesizer fabricated in a 130 nm CMOS technology is presented for the application of an FM tuner. A low noise filter, occupying a small die area and decreasing the output noise, is integrated on a chip. A quantization noise suppression technique, using a reduced step size of the frequency divider, is also adopted. The proposed synthesizer needs no off-chip components and occupies an area of 0.7 mm2. The in-band phase noise （from 10 to 100 kHz） below -108 dBc/Hz and out-of-band phase noise of -122.9 dBc/Hz （at 1 MHz offset） are measured with a loop bandwidth of 200 kHz. The quantization noise suppression technique reduces the in-band and out-of band phase noise by 15 dB and 7 dB respectively. The integrated RMS phase error is no more than 0.48°. The proposed synthesizer consumes a total power of 7.4 mW and the frequency resolution is less than 1 Hz.     

一种应用于WiMAX协议的全集成3.5GHzCMOS功率驱动放大器

A fully integrated CMOS differential power amplifier driver(PAD) is proposed for WiMAX applications. In order to fulfill the differential application requirements,a transmission line transformer is used as the output matching network.A differential inductance constitutes an inter-stage matching network.Meanwhile,an on chip balun realizes input matching as well as single-end to differential conversion.The PAD is fabricated in a 0.13μm RFCMOS process.The chip size is 1.1×1.1 mm~2 with all of the matching network integrated on chip. The saturated power is around 10 dBm and power gain is about 12 dB.     

8位12MS/s带片上参考电压的异步逐次逼近模数转换器

This paper proposes an 8 bit asynchronous successive approximation register ADC for wireless transceivers.A split capacitor DAC is used to reduce power and area consumption and the value of the split capacitor is calculated theoretically to ensure linearity.Asynchronous control logic is proposed to eliminate the high internal clocks and significantly speeds up the successive approximation algorithm.An on-chip reference with a fully integrated buffer and decoupling capacitor is adopted for avoiding an extra pin for the off-chip reference. The prototype,fabricated in UMC 0.18μm CMOS technology,achieves an effective number of bits of 7.64 bits at a sampling frequency of 12 MS/s.The total power consumption is 0.918 mW for a 1.8 V supply,while the onchip reference consumes 53%of the total power.It achieves a figure of merit of 180 fJ/conv-step,excluding the reference’s power consumption.     

一种用于UHF RFID标签的超低功耗数字处理机设计

A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed. This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption. By applying methods like system-level power management, global clock gating and low voltage implementation, the total power of the design is reduced to a few microwatts. In addition, an innovative way for the design of a true RNG is presented, which contributes to both low power and secure data transaction. The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows. The design fits different CMOS technologies and has been taped out using the 2P4M 0.35 μm process of Chartered Semiconductor.     

一种平均电流模式控制的单电感双输出型开关电源转换器

An integrated single-inductor dual-output （SIDO） switching DC-DC converter is presented. The outputs are specified with 1.2 V/400 mA and 1.8 V/200 mA. A decoupling small signal model is proposed to analyze the multi-loop system and to design the on-chip compensators. An average current control mode is introduced with lossless, continuous current detection. The converter has been fabricated in a 0.25μm 2P4M CMOS process. The power efficiency is 86% at a total output power of 840 mW while the output ripples are about 40 mV at an oscillator frequency of 600 kHz.     

A power scalable PLL frequency synthesizer for high-speed △-∑ ADC

A 35-130 MHz/300-360 MHz phase-locked loop frequency synthesizer for △-∑ analog-to-digital con- verter （ADC） in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode （300-360 MHz） or in low-power mode （35-130 MHz） to satisfy the ADC＇s requirements. To switch between these two modes, a high frequency GHz LC VCO followed by a divided-by-four frequency divider and a low frequency ring VCO followed by a divided-by-two frequency divider are integrated on-chip. The measured results show that the fre- quency synthesizer achieves a phase-noise of-132 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 1.12 ps with 1.74 mW power consumption from a 1.2 V power supply in low phase-noise mode. In low-power mode, the frequency synthesizer achieves a phase-noise of-112 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 7.23 ps with 0.92 mW power consumption from a 1.2 V power supply.     

基于SiGe BiCMOS技术的低功耗23G VCO

A 23 GHz voltage controlled oscillator(VCO) with very low power consumption is presented.This paper presents the design and measurement of an integrated millimeter wave VCO.This VCO employs an on-chip inductor and MOS varactor to form a high Q resonator.The VCO RFIC was implemented in a 0.18μm 120 GHz f_t SiGe hetero-junction bipolar transistor(HBT) BiCMOS technology.The VCO oscillation frequency is around 23 GHz,targeting at the ultra wideband(UWB) and short range radar applications.The core of the VCO circuit consumes 1 mA current from a 2.5 V power supply and the VCO phase noise was measured at around -94 dBc/Hz at a 1 MHz frequency offset.The FOM of the VCO is -177 dBc/Hz.     

一种应用于RFID标签的新型功率放大器设计

A novel matching method between the power amplifier (PA) and antenna of an active or semi-active RFID tag is presented. A PCB dipole antenna is used as the resonance inductor of a differential power amplifier. The total PA chip area is reduced greatly to only 240 × 70 μm² in a 0.18 μm CMOS process due to saving two on-chip integrated inductors. Operating in class AB with a 1.8 V supply voltage and 2.45 GHz input signal, the PA shows a measured output power of 8 dBm at the 1 dB compression point.     

A micromachined inline type microwave power sensor with working state transfer switches

A wideband 8-12 GHz inline type microwave power sensor,which has both working and non-working states,is presented.The power sensor measures the microwave power coupled from a CPW line by a MEMS membrane.In order to reduce microwave losses during the non-working state,a new structure of working state transfer switches is proposed to realize the two working states.The fabrication of the power sensor with two working states is compatible with the GaAs MMIC(monolithic microwave integrated circuit) process.The experimental results show that the power sensor has an insertion loss of 0.18 dB during the non-working state and 0.24 dB during the working state at a frequency of 10 GHz.This means that no microwave power has been coupled from the CPW line during the non-working state.     

应用于无源超高频射频识别卡芯片的能量提取电路建模与分析

Modeling and analysis of far field power extraction circuits for passive UHF RF identification （RFID） applications are presented. A mathematical model is derived to predict the complex nonlinear performance of UHF voltage multiplier using Schottky diodes. To reduce the complexity of the proposed model, a simple linear approximation for Schottky diode is introduced. Measurement results show considerable agreement with the values calculated by the proposed model. With the derived model, optimization on stage number for voltage multiplier to achieve maximum power conversion efficiency is discussed. Furthermore, according to the Bode-Fano criterion and the proposed model, a limitation on maximum power up range for passive UHF RFID power extraction circuits is also studied.     

An 8 GHz high power AlGaN/GaN HEMT VCO

A high power X-band hybrid microwave integrated voltage controlled oscillator(VCO) based on Al-GaN /GaN HEMT is presented.The oscillator design utilizes a common-gate negative resistance structure with open and short-circuit stub microstrip lines as the main resonator for a high Q factor.The VCO operating at 20 V drain bias and-1.9 V gate bias exhibits an output power of 28 dBm at the center frequency of 8.15 GHz with an efficiency of 21%.Phase noise is estimated to be -85 dBc/Hz at 100 kHz offset and -1...     

无源超高频射频识别标签中浅调制信号的检测

In a typical RFID system the reader transmits modulated RF power to provide both data and energy for the passive transponder. Low modulation index RF energy is preferable for an adequate tag power supply and increase in communication range but gives rise to difficulties for near-field conventional demodulation. Therefore, a novel ASK demodulator for minimum 20% modulation index RF signal detection over a range of 23 dB is presented. Thanks to the proposed innovative divisional linear conversion from the power into voltage signal, the detection sensitivity is ensured over a wide power range with low power consumption of 8.6 μW. The chip is implemented in UMC 0.18μm mix-mode CMOS technology, and the chip area is 0.06 mm^2.     

Research on optimizing the noise figure of low noise amplifier method via bias and frequency

In this paper,we present the design of an integrated low noise amplifier(LNA)for wireless local area network(WLAN)applications in the 5.15-5.825 GHz range using a SiGe BiCMOS technology.A novel method that can determine both the optimum bias point and the frequency point for achieving the minimum noise figure is put forward.The method can be used to determine the optimum impedance over a relevant wider operating frequency range.The results show that this kind of optimizing method is more suitable for the WLAN circuits design.The LNA gain is optimized and the noise figure(NF)is reduced.This method can also achieve the noise match and power match simultaneously.This proposal is applied on designing a LNA for IEEE 802.11a WLAN.The LNA exhibits a power gain large than 16 dB from 5.15 to 5.825 GHz range.The noise figure is lower than 2 dB.The OIP3 is 8 dBm.Also the LNA is matched to 50 Ω input impedance with 6 mA DC current for differential design.