用于高能物理实验电子读出芯片的低噪声锁相环芯片设计

基于TSMC 180 nm工艺设计并流片测试了一款用于高能物理实验的电子读出系统的低噪声、低功耗锁相环芯片。该芯片主要由鉴频鉴相器、电荷泵、环路滤波器、压控振荡器和分频器等子模块组成,在锁相环电荷泵模块中,使用共源共栅电流镜结构精准镜像电流以减小电流失配和用运放钳位电压进一步减小相位噪声。测试结果表明,该锁相环芯片在1.8 V电源电压、输入50 MHz参考时钟条件下,可稳定输出200 MHz的差分时钟信号,时钟均方根抖动为2.26 ps(0.45 mUI),相位噪声在1 MHz频偏处为-105.83 dBc/Hz。芯片整体功耗实测为23.4 mW,锁相环核心功耗为2.02 mW。     

用传输门VCO和动态PFD设计低功耗CMOS琐相环

锁相环（PLL）是VLSI系统的重要单元电路之一,为了实现高速低功耗的CMOS锁相环,用传输门VCO和动态反相器PFD电路设计CMOS锁相环。传输门结构VCO具有高速、低电压和低功耗的特性,而动态反相器PFD具有功耗低和面积小的特点。SPICE模拟表明,当电源电压为2．5V时,基于0．6μmCMOS工艺设计的CMOS锁相环电路,工作频率高达1000MHz,而功耗低于50mW。     

A low jitter, low spur multiphase phase-locked loop for an IR-UWB receiver

A low jitter,low spur multiphase phase-locked loop(PLL) for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator(VCO) is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the l...     

GPS射频接收芯片中低功耗压控振荡器的设计

设计了一种应用于GPS射频接收芯片的低功耗环形压控振荡器.环路由5级差分结构的放大器构成.芯片采用TSMC 0.18 μm CMOS工艺,核心电路面积0.25 mm×0.05 mm.测试结果表明,采用1.75 V电源电压供电时,电路的功耗约为9.2 mW,振荡器中心工作频率为62 MHz,相位噪声为-89.39 dBc/Hz @ 1 MHz,该VCO可应用于锁相环和频率合成器中.     

一种基于55nmCMOS工艺，输出频率0.1G-1.5G Hz的低抖动锁相环

本文设计了一种0.1G-1.5GHz,3.07pS RMS 抖动的多相位输出锁相环。通过引入双路径电荷泵,极大的减小了锁相环中的低通滤波器的尺寸。基于指定的功耗约束,提出了一种新颖的压控振荡器、电荷泵与鉴频鉴相器的尺寸优化方法,使用该方法,每个模块输出相位噪声减小了约3-6dBc/Hz。该锁相环在55nm的工艺下流片,集成了16pF的MOM电容,占用面积仅为0.05平方毫米。输出1.5GHz信号时,功耗2.8mW,相位噪声为-102dBc/Hz@1MHz。     

基于电感电容振荡器的电荷泵锁相环的设计

设计并实现了一种采用电感电容振荡器的电荷泵锁相环,分析了锁相环中鉴频/鉴相器(PFD)、电荷泵(CP)、环路滤波器(LP)、电感电容压控振荡器(VCO)的电路结构和设计考虑。锁相环芯片采用0.13μm MS&RF CMOS工艺制造。测试结果表明,锁相环锁定的频率为5.6～6.9 GHz。在6.25 GHz时,参考杂散为-51.57 dBc;1 MHz频偏处相位噪声为-98.35 dBc/Hz;10 MHz频偏处相位噪声为-120.3 dBc/Hz;在1.2 V/3.3 V电源电压下,锁相环的功耗为51.6 mW。芯片总面积为1.334 mm2。     

应用于60-GHz无线通信的全差分锁相环频率综合器

A 40-GHz phase-locked loop(PLL) frequency synthesizer for 60-GHz wireless communication applications is presented. The electrical characteristics of the passive components in the VCO and LO buffers are accurately extracted with an electromagnetic simulator HFSS. A differential tuning technique is utilized in the voltage controlled oscillator(VCO) to achieve higher common-mode noise rejection and better phase noise performance. The VCO and the divider chain are powered by a 1.0 V supply while the phase-frequency detector(PFD)and the charge pump(CP) are powered by a 2.5 V supply to improve the linearity. The measurement results show that the total frequency locking range of the frequency synthesizer is from 37 to 41 GHz, and the phase noise from a 40 GHz carrier is –97.2 d Bc/Hz at 1 MHz offset. Implemented in 65 nm CMOS, the synthesizer consumes a DC power of 62 m W, including all the buffers.     

一种带有升压电路的0.5V 3GHz低功耗LC VCO设计

采用标准的0.13μm CMOS工艺实现了0.5V电源电压,3GHz LC压控振荡器。为了适应低电压工作,并实现低相位噪声,该压控振荡器采用了NMOS差分对的电压偏置振荡器结构,去除尾电流,以尾电感代替,采用感性压控端,增加升压电路结构使变容管的一端升压,这样控制电压变化范围得到扩展。测试结果显示,当电源电压为0.5V,振荡频率为3.126GHz时,在相位噪声为-113.83dBc/Hz@1MHz,调谐范围为12%,核心电路功耗仅1.765mW,该振荡器的归一化品质因数可达-186.2dB,芯片面积为0.96mm×0.9mm。     

A Quantization Noise Pushing Technique for $DeltaSigma$ Fractional- $N$ Frequency Synthesizers

This paper demonstrates our proposed quantization noise pushing technique, which moves the quantization noise to higher frequencies and utilizes the low-pass characteristic of the phased-lock loop (PLL) to further suppress the quantization noise. In addition, it can separate the operating frequency of the DeltaSigma modulator and the comparison frequency of the phase/frequency detector (PFD) so as to reduce the loop gain of the PLL and lower the in-band phase noise. This synthesizer was fabricated using the UMC 0.18-mum CMOS process. The chip area measures 0.85 mm². The supply voltage is 2 V, corresponding to a total power consumption of 26.8 mW. The experimental results show that, with this technique, the in-band phase noise can be lowered by 12 dB, while the out-of-band phase noise can be reduced by more than 15 dB, compared to a synthesizer with the same PFD comparison frequency.     

A 5.7–6.0 GHz CMOS PLL with low phase noise and −68 dBc reference spur

This paper presents a 5.7–6.0 GHz Phase-Locked Loop (PLL) design using a 130 nm 2P6M CMOS process. We propose to suppress reference spur through reducing the current mismatch in charge pump (CP), controlling the delay time in phase frequency detector (PFD), and using a smaller VCO gain (KVCO). With a reference frequency of 32.768 MHz, chip measurement results show that the frequency tuning range is 5.7–6.0 GHz, the reference spur is −68 dBc, the phase noise levels are −109 dBc/Hz and −135 dBc/Hz at 1 MHz and 10 MHz offset respectively for 5.835 GHz. Compared with existing designs in the literature, this work’s reference spur is improved by at least 17% and its phase noise is the lowest. Under a 1.5 V supply voltage, the power dissipation with an output buffer of the PLL is 12 mW.     

A 0.13μm CMOS △∑ fractional-N frequency synthesizer for WLAN transceivers

A fractional-N frequency synthesizer fabricated in a 0.13 μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network (WLAN) transceivers.A monolithic LC voltage controlled oscillator (VCO) is implemented with an on-chip symmetric inductor.The fractional-N frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping (MASH) △ ∑ modulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm2.     

A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 Voperation

This paper describes a phase-locked loop (PLL) based frequency synthesizer. The voltage-controlled oscillator (VCO) utilizing a ring of single-ended current-steering amplifiers (CSA) provides low noise, wide operating frequencies, and operation over a wide range of power supply voltage. A programmable charge pump circuit automatically configures the loop gain and optimizes it over the whole frequency range. The measured PLL frequency ranges are 0.3-165 MHz and 0.3-100 MHz at 5 V and 3 V supplies, respectively (the VCO frequency is twice PLL output). The peak-to-peak jitter is 81 ps (13 ps rms) at 100 MHz. The chip is fabricated with a standard 0.8-μm n-well CMOS process     

一种DC-DC升压型开关电源的低压启动方案

设计了一种DC-DC升压型开关电源的低压启动电路,该电路采用两个在不同电源电压范围内工作频率较稳定的振荡器电路,利用电压检测模块进行合理的切换,解决了低输入电压下电路无法正常工作的问题,并在0.5μm CMOS工艺库（VthN=0.72 V,VthP=-0.97 V）下仿真。仿真结果表明,在0.8 V低输入电压时,通过此升压型开关电源,可以将VDD升高至3.3 V。     

低噪声、低功耗CMOS电荷泵锁相环设计

设计了一种 1 .8V、0 .1 8μm工艺的低噪声低功耗锁相环电路 ,其采用 CSA(Current Steer Amplifier)架构的压控振荡器 (VCO)。整个电路功耗低 ,芯片面积为 1 60 μm× 1 2 0 μm,对电源和衬底噪声抑制能力强。经过Spice模拟表明 ,在有电源噪声的情况下 ,输出 5 0 0 MHz时钟时周对周抖动小于 41 ps,功耗为 2 .8m W,最终与芯片的量测结果基本一致     

A voltage-controlled oscillator with an ultra-low supply voltage and its application to a fractional-N phase-locked loop

With feature size scaling, the supply voltage of digital circuits is becoming lower and lower. As a result, the supply voltage of analogue and RF circuits must also be reduced for system on chip (SoC) realisation. This article proposes an ultra-low-supply voltage-controlled oscillator (ULSVCO) and designs a sigma–delta fractional-N frequency synthesiser which adopts such ULSVCO. A mathematical phase-noise model is built here to describe the noise performance of the low-supply voltage-controlled oscillator (VCO). The substrate of the cross-coupled NMOSFETs in the proposed ULSVCO is not grounded but connected to the supply to further reduce the supply voltage. Implemented in 0.18 μm CMOS technology, the proposed ULSVCO can be operated at a supply voltage as low as 0.41 V, the central frequency is set to 1.55 GHz, the phase noise is ?116 dBc/Hz@1.0 MHz. The minimum supply voltage is decreased by about 11% after our idea is adopted and the power consumption of the ULSVCO is only 1.04 mW. With the proposed ULSVCO, we design a sigma–delta-modulator (SDM) fractional-N phase-locked loop frequency synthesiser, which has a 1.43–1.75 GHz frequency tuning range. When the loop bandwidth is set to 100 KHz, the phase noise of our PLL is ?110 dBc/Hz@1.0 MHz.     

高精度低噪声基准电压源的设计

利用反向带隙电压原理,采用基于CMOS阈值电压的自偏置共源共栅电流镜技术,设计了一种低压低噪声基准电压源.该电压基准源没有外加滤波电容的情况下,通过双极型晶体管大的输出阻抗特性,实现了更低的噪声输出,提高了输出电压的精度.Hspice仿真结果表明,在0.95V电源电压下,输出基准电压为233.9 mV,温度系数为7.6...     

A fully integrated low-noise 1-GHz frequency synthesizer design formobile communication application

This paper describes a fully monolithic phase-locked loop (PLL) frequency synthesizer circuit implemented in a standard 0.8-μm CMOS technology. To be immune to noise, all the circuits in the synthesizer use differential schemes with the digital parts designed by static logic. The experimental voltage controlled oscillator (VCO) has a center frequency of 800 MHz and a tuning range of ±25%. The measured frequency synthesizer performance has a frequency range from 700 MHz to 1 GHz with -80 dBc/Hz phase noise at a 100 kHz carrier offset. With an active area of 0.34 mm², the test chip consumes 125 mW at maximum frequency from a 5 V supply. The only external components are the supply decoupling capacitors and a passive filter     

A low phase noise and low power 3–5 GHz frequency synthesizer in 0.18 µm CMOS technology

A low power frequency synthesizer for WLAN applications is proposed in this paper. The NMOS transistor-feedback voltage controlled oscillator (VCO) is designed for the purpose of decreasing phase noise. TSPC frequency divider is designed for widening the frequency range with keeping low the power consumption. The phase frequency detector (PFD) with XOR delay cell is designed to have the low blind and dead zone, also for neutralizing the charge pump (CP) output currents; the high gain operational amplifier and miller capacitors are applied to the circuit. The frequency synthesizer is simulated in 0.18 µm CMOS technology while it works at 1.8 V supply voltage. The VCO has a phase noise of −136 dBc/Hz at 1 MHz offset. It has 10.2% tuning range. With existence of a frequency divider in the frequency synthesizer loop the output frequency of the VCO can be divided into the maximum ratio of 18. It is considered that the power consumption of the frequency synthesizer is 4 mW and the chip area is 10,400 µm².     

CMOS ring VCO for UHF RFID readers

A complementary metal oxide semiconductor (CMOS) voltage controlled ring oscillator for ultra high frequency (UHF) radio frequency identification (RFID) readers has been realized and characterized. Fabricated in charter 0.35 μm CMOS process, the total chip size is 0.47×0.67 mm2. While excluding the pads, the core area is only 0.15×0.2 mm2. At a supply voltage of 3.3 V, the measured power consumption is 66 mW including the output buffer for 50 Ω testing load. This proposed voltage-controlled ring oscillator exhibits a low phase noise of - 116 dBc/Hz at 10 MHz offset from the center frequency of 922.5 MHz and a lower tuning gain through the use of coarse/fine frequency control.     

A 5 GHz CMOS frequency synthesizer with novel phase-switching prescaler and high-Q LC-VCO

A phase-locked loop(PLL) frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator(VCO) is presented.The phase-switching prescaler with a novel modulus control mechanism is much more robust on process variations.The Q factor of the inductor,I-MOS capacitors and varactors in the VCO are optimized.The proposed frequency synthesizer was fabricated by SMIC 0.13μm 1P8M MMRF CMOS technology with a chip area of 1150×2500μm~2.When locking at 5 GHz,the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at a 1 MHz offset is -122.45 dBc/Hz.