负偏置温度不稳定性导致单粒子瞬态脉冲的压缩与展宽

摘要：本文基于3D TCAD 器件模拟,研究了130nm体硅工艺下,负偏置温度不稳定性（NBTI）对单粒子瞬态（SET）脉冲的影响。研究结果表明：当粒子轰击高输入反相器的PMOS管时,NBTI能够导致所产生的SET脉冲的宽度和幅度随时间不断压缩,当粒子轰击低输入反相器的NMOS管时,NBTI能够导致所产生的SET脉冲的宽度和幅度随时间不断展宽。基于研究结果,本文首次提出：NBTI对粒子轰击NMOS管所产生的SET脉冲的影响已经十分严重,在进行抗辐照加固设计时必须考虑NBTI所造成的影响。     

NBTI效应导致SET脉冲在产生与传播过程中的展宽

本文研究了负偏置温度不稳定性(NBTI)对单粒子瞬态(SET)脉冲产生与传播过程的影响.研究结果表明:NBTI能够导致SET脉冲在产生与传播的过程中随时间而不断展宽.本文还基于工艺计算机辅助设计模拟软件(TCAD)进行器件模拟,提出了一种在130nm体硅工艺下,计算SET脉冲宽度的解析模型,并结合NBTI阈值电压退化的...     

Buffer单元单粒子效应及其若干影响因素研究

基于标准0.13μm工艺使用Sentaurus TCAD软件采用3D器件/电路混合模拟方式仿真了buffer单元的单粒子瞬态脉冲。通过改变重离子的入射条件,得到了一系列单粒子瞬态电流脉冲(SET)。分析了LET值、入射位置、电压偏置等重要因素对SET峰值和脉宽的影响。研究发现,混合模式仿真中的上拉补偿管将导致实际电路中SET脉冲的形状发生明显的变化。     

Line-edge roughness induced single event transient variation in SOI FinFETs

The impact of process induced variation on the response of SOI FinFET to heavy ion irradiation is studied through 3-D TCAD simulation for the first time. When FinFET biased at OFF state configuration (V_gs=0, V_ds=V_dd) is struck by a heavy ion, the drain collects ionizing charges under the electric field and a current pulse (single event transient, SET) is consequently formed. The results reveal that with the presence of line-edge roughness (LER), which is one of the major variation sources in nano-scale FinFETs, the device-to-device variation in terms of SET is observed. In this study, three types of LER are considered: type A has symmetric fin edges, type B has irrelevant fin edges and type C has parallel fin edges. The results show that type A devices have the largest SET variation while type C devices have the smallest variation. Further, the impact of the two main LER parameters, correlation length and root mean square amplitude, on SET variation is discussed as well. The results indicate that variation may be a concern in radiation effects with the down scaling of feature size.     

双极电压比较器LM311电离总剂量与单粒子瞬态协同效应研究

本文研究了高、低电平输出偏置条件下双极电压比较器LM311的电离总剂量（Total Ionizing Dose,TID）—单粒子瞬态（Single Event Transient,SET）的协同效应.实验结果表明,高电平输出偏置条件下累积总剂量后的LM311的SET会受到明显抑制,主要表现为瞬态脉冲宽度减小,SET幅值变小.低电平输出偏置条件下累积总剂量后的LM311的SET有促进作用,主要表现为瞬态脉冲宽度增大,SET幅值变大.与高电平输出偏置条件相比,LM311在低电平输出偏置条件下对SET不敏感.发现TID诱发的界面态陷阱电荷和氧化物陷阱电荷是TID-SET协同抑制效应出现的根本原因.     

Single event transient pulse width measurement of 65-nm bulk CMOS circuits

Heavy ion results of a 65-nm CMOS SET pulse width testchip are given. The influences of device threshold voltage, temperature and well separation on pulse width are discussed. Experimental data implied that the low device threshold, high temperature and well speraration would contribute to wider SET. The multi-peak phenomenon in the distribution of SET pulse width was first observed and its dependence on various factors is also discussed.     

基于四值脉冲参数模型的单粒子瞬态传播机理与软错误率分析方法

随着工艺尺寸的不断缩小,由单粒子瞬态(Single Event Transient, SET)效应引起的软错误已经成为影响宇航用深亚微米VLSI电路可靠性的主要威胁,而SET脉冲的产生和传播也成为电路软错误研究的热点问题。通过研究SET脉冲在逻辑链路中的传播发现：脉冲上升时间和下降时间的差异能够引起输出脉冲宽度的展宽或衰减;脉冲的宽度和幅度可决定其是否会被门的电气效应所屏蔽。该文提出一种四值脉冲参数模型可准确模拟SET脉冲形状,并采用结合查找表和经验公式的方法来模拟SET脉冲在电路中的传播过程。该文提出的四值脉冲参数模型可模拟SET脉冲在传播过程中的展宽和衰减效应,与单参数脉冲模型相比计算精度提高了2.4%。该文应用基于图的故障传播概率算法模拟SET脉冲传播过程中的逻辑屏蔽,可快速计算电路的软错误率。对ISCAS89及ISCAS85电路进行分析的实验结果表明：该方法与HSPICE仿真方法的平均偏差为4.12%,计算速度提升10000倍。该文方法可对大规模集成电路的软错误率进行快速分析。     

运放和光耦的单粒子瞬态脉冲效应

利用脉冲激光模拟单粒子效应实验装置研究了通用运算放大器LM124J和光电耦合器HCPL5231的单粒子瞬态脉冲(SET)效应,获得了LM124J工作在电压跟随器模式下的瞬态脉冲波形参数与等效LET值的关系,甄别出该器件SET效应的敏感节点分布.初步分析了SET效应产生的机理.以HCPL5231为例,首次利用脉冲激光测试了光电耦合器的单粒子瞬态脉冲幅度、宽度与等效LET值的关系,并尝试测试了该光电耦合器的SET截面,实验结果与其他作者利用重离子加速器得到的数据符合较好,证实了脉冲激光测试器件单粒子效应的有效性.     

Experimental research of heavy ion and proton induced single event effects for a Bi-CMOS technology DC/DC converter

This paper tested and analyzed heavy ion and proton induced single event effects (SEE) of a commercial DC/DC converter based on a 600 nm Bi-CMOS technology. Heavy ion induced single event transients (SET) testing has been carried out by using the Beijing HI-13 tandem accelerator at China Institute of Atomic Energy. Proton test has been carried out by using the Canadian TRIUMF proton accelerator. Both SET cross section versus linear energy transfer (LET) and proton energy has been measured. The main study conclusions are: (1) the DC/DC is both sensitive to heavy ion and proton radiations although at a pretty large feature size (600 nm), and threshold LET is about 0.06 MeV·mg/cm²; (2) heavy ion SET saturation cross section is about 5 magnitudes order larger than proton SET saturation cross section, which is consistent with the theory calculation result deduced by the RPP model and the proton nuclear reaction model; (3) on-orbit soft error rate (SER) prediction showed, on GEO orbit, proton induced SERs calculated by the heavy ion derived model are 4-5 times larger than those calculated by proton test data.     

一种低压差线性稳压器的单粒子瞬态失效分析和加固设计

随着集成电路特征尺寸的不断缩减,CMOS集成电路的单粒子效应问题越来越严重。为了提高低压差线性稳压器(LDO)的单粒子瞬态(SET)效应加固效果,该文通过SPICE电路仿真和重离子实验研究了一种28 nm CMOS工艺LDO的SET失效机制,并研究了关键器件尺寸大小对SET脉冲的影响,提出一种有效的LDO加固方法。SPICE电路仿真发现这种LDO的敏感节点主要位于误差放大器(EA)内部。功率管(MOSFET)栅极节点的环路滤波电容会明显地影响单粒子瞬态脉冲的幅度,也会轻微地影响单粒子瞬态脉冲的宽度。误差放大器内部关键节点的器件尺寸会影响稳压器输出的单粒子瞬态脉冲的幅度和宽度。通过增加功率管(MOSFET)栅极节点电容和调整误差放大器内部相关节点器件尺寸的方法对LDO进行了SET加固设计。电路仿真和重离子实验结果表明这种加固方法能够有效地降低LDO输出的单粒子瞬态脉冲的幅度和宽度。     

低失调电压双极运放的单粒子瞬态特性研究

在Ne、Fe、Kr、Xe、Ta五种重离子入射条件下获得了运放的SET幅值-宽度分布,发现SET脉冲具有宽、窄两种形态。在SET幅值-宽度特性基础上,采用概率密度方法获得了任意SET阈值下散射截面与LET的关系。考虑入射深度与器件敏感区域的匹配,根据产生的电荷量,可对重离子-激光的SET进行关联,以便获得等效重离子的激光能量。激光与重离子的对比试验表明,选取恰当的激光能量,能够反映重离子产生的SET幅值。研究结果为双极模拟集成电路抗SET选型评估及激光试验条件的选取提供了参考。     

纳米CMOS电路的单粒子瞬态影响因素研究

进入纳米尺度后,单粒子瞬态(SET)成为高能粒子入射VLSI产生的重要效应,准确、可靠的SET模拟对评估VLSI的可靠性有着重要的影响。以反相器为例,针对脉冲峰值和半高全宽两个指标,研究了电路模拟中影响SET的因素,主要有电流脉冲幅值、脉冲宽度、负载电容、环境温度及器件尺寸。通过对45和65 nm两种技术节点下的电路的仿真,研究了这些因素对SET的影响,并探讨了可能的原因。结果显示,这些因素对SET的影响趋势和程度有很大的差异,且器件尺寸越小,这些因素对SET的影响越显著。通过设置合适的参数,可以实现电路的抗辐射加固。     

Test Circuit for Measuring Pulse Widths of Single-Event Transients Causing Soft Errors

A novel on-chip test circuit to measure single-event transient (SET) pulse widths has been developed and implemented in IBM 130-nm and 90-nm processes for characterizing logic soft errors. Test measurements with heavy ions and alpha particles show transient widths ranging from 100 ps to over 1 ns, comparable to legitimate logic signals in such technologies. Design options to limit the SET pulse width and hence to mitigate soft errors are evaluated with the test circuit to demonstrate the effectiveness of such design techniques.      

Improved on-chip self-triggered single-event transient measurement circuit design and applications

Single-event transient (SET) induced soft errors are becoming more and more a threat to the reliability of electronic systems in space. The SET pulse width is an important parameter characterizing the possibility of an SET being latched by a sequential element such as a flip-flop. This paper improves the widely used on-chip self-triggered SET measurement circuit by changing it from a single SET measurement module to a combination of two modules. One module is responsible for measuring narrow SET pulse widths while the other is responsible for measuring modest and wide SET pulse widths. In this way, the range of measurable SET pulse width is increased. Pulsed laser facility is used to simulate single-event transients induced by single-particles. Experimental results demonstrate that the minimum accurately measured SET pulse width is decreased from 166.5 ps to 33.3 ps after adopting the proposed design when compared with the original one. SET pulse width broadening effect was also observed using the measurement system. The broadening factor was measured to be 0.123–0.143 ps/inverter.     

65 nm体硅工艺NMOS中单粒子多瞬态效应的研究

针对NMOS场效应晶体管由重离子辐射诱导发生的单粒子多瞬态现象,参考65 nm体硅CMOS的单粒子瞬态效应的试验数据,采用TCAD仿真手段,搭建了65 nm体硅NMOS晶体管的TCAD模型,并进一步对无加固结构、保护环结构、保护漏结构以及保护环加保护漏结构的抗单粒子瞬态效应的机理和能力进行仿真分析。结果表明,NMOS器件的源结和保护环结构的抗单粒子多瞬态效应的效果更加明显。     

运放和光耦的单粒子瞬态脉冲效应

利用脉冲激光模拟单粒子效应实验装置研究了通用运算放大器LM124J和光电耦合器HCPL5231的单粒子瞬态脉冲（SET）效应,获得了LM124J工作在电压跟随器模式下的瞬态脉冲波形参数与等效LET值的关系,甄别出该器件SET效应的敏感节点分布.初步分析了SET效应产生的机理.以HCPL5231为例,首次利用脉冲激光测试了光电耦合器的单粒子瞬态脉冲幅度、宽度与等效LET值的关系,并尝试测试了该光电耦合器的SET截面,实验结果与其他作者利用重离子加速器得到的数据符合较好,证实了脉冲激光测试器件单粒子效应的有效性.     

Modeling and analysis of single-event transients in charge pumps

It has been shown that charge pumps (CPs) dominate single-event transient (SET) responses of phaselocked loops (PLLs). Using a pulse to represent a single event hit on CPs, the SET analysis model is established and the characteristics of SET generation and propagation in PLLs are revealed. An analysis of single event transients in PLLs demonstrates that the settling time of the voltage-controlled oscillators (VCOs) control voltage after a single event strike is strongly dependent on the peak control voltage deviation, the SET pulse width, and the settling time constant. And the peak control voltage disturbance decreases with the SET strength or the filter resistance. Furthermore, the analysis in the proposed PLL model is confirmed by simulation results using MATLAB and HSPICE,respectively.     

0.18μm NMOS的重离子单粒子瞬态脉冲的仿真模拟

为了详细地了解纳米MOS电路中单粒子瞬变电荷收集机理,利用ISETCAD软件仿真二维模拟0.18μm NMOS的单粒子瞬态脉冲。通过进行三种不同的电路连接方式和不同的粒子注入位置的仿真,得到了一系列单粒子瞬态电流脉冲(SET)与时间的关系曲线。分析了不同电路连接方式和注入位置对SET的峰值和脉宽的影响。为下一步建立SET的精确模型进行SET效应的模拟做基础的研究。     

A New Analytical Model of SET Latching Probability for Circuits Experiencing Single- or Multiple-Cycle Single-Event Transients

As technology scales down, more single-event transients (SETs) are expected to occur in combinational circuits and thus contribute to the increase of soft error rate (SER). We propose a systematic analysis method to precisely model the SET latching probability. Due to the decreased critical charge and shortened pipeline stage, the SET duration time is likely to exceed one clock cycle. In previous work, the SET latching probability is modeled as a function of SET pulse width, setup and hold times, and clock period for single-cycle SETs. Our analytical model does not only include new dependent parameters such as SET injection location and starting time, but also precisely categorizes the SET latching probabilities for different parameter ranges. The probability of latching multiple-cycle SETs is specifically analyzed in this work to address the increasing ratio of SET pulse width over clock period. We further propose a method that exploits the boundaries of those dependent parameters to accelerate the SER estimation. Simulation results show that the proposed analysis method achieves up to 97% average accuracy, which is applicable for both single- and multiple-cycle SETs. Our case studies on ISCAS’85 benchmark circuits confirm our analysis on the impact of SET injection location and starting time on the SET latching probability. By exploiting our analytical model, we achieve up to 78% simulation time reduction on the process of SET latching probability and SER estimation, compared with Monte-Carlo simulation.     

0.18um NMOS的重离子单粒子瞬态脉冲的仿真模拟

摘要：为了详细的了解纳米MOS电路中单粒子瞬变电荷收集机理,利用ISETCAD软件仿真二维模拟0.18um NMOS的单粒子瞬态脉冲。通过进行三种不同的电路连接方式和不同的粒子注入位置的仿真,得到了一系列单粒子瞬态电流脉冲（SET）与时间的关系曲线。分析了不同电路连接方式和注入位置对SET的峰值和脉宽的影响。为下一步建立SET的精确模型进行SET效应的模拟做基础的研究。