A 3-5 GHz TH-UWB transmitter in 0.18-μm RF CMOS technology

5 mV at a 50 Ω load from a 1.8-V supply, the return loss (S11) at the output port is less than -10 dB, and the chip size is 0.7 × 0.8 mm2, with a power consumption of 12.3 mW.     

A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18μm CMOS for OFDM-UWB

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single （D2S） converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18μm RF CMOS process with an area of 1.74 mm^2 and only consumes 32 mA current （at 1.8 V） including the test associated parts.     

5 GHz 0.18-μm CMOS 可编程分频器

提出了一种2.4GHz ZigBee 应用的可编程分频器,其分频模值在2403-2480之间变化。该分频器基于双模分频器和吞咽计数器架构,功耗和面积得到了有效降低。芯片采用0.18-μm CMOS混合信号工艺实现,当输入信号达到7.5dBm时,分频器可正常工作的频率范围覆盖1-7.4 GHz,在100KHz频偏处的输出相位噪声为-125.3dBc/Hz。分频器核心电路消耗电流4.3mA（1.8V电源电压）,核心面积0.015mm2。测试结果表明该可编程分频器能很好的应用在所需的频率综合器中.     

一种用于3-5GHz IR-UWB的0.18um CMOS BPSK 调制发射机

This paper presents a transmitter IC with BPSK modulation for an ultra-wide band system. It is based on up-conversion with a high linearity passive mixer. Unlike the traditional BPSK modulation scheme, the local oscillator (LO) is modulated by the baseband data instead of the pulse. The chip is designed and fabricated by standard 0.18 μ m CMOS technology. The transmitter achieves a high data rate up to 400 Mbps. The amplitude of the pulse can be adjusted by the amplitude of the LO and the bias current of the driver amplifier. The maximum peak-to-peak amplitude of the pulse is 600 mV. It consumes only 20.3 mA current with a supply voltage of 1.8 V when transmitting a pulse at the maximum data rate. The energy efficiency is 91.4 pJ/pulse. The die area is 1.4 × 1.4 mm².     

A 0.18μm CMOS 3-5 GHz broadband flat gain low noise amplifier

A 3-5 GHz broadband flat gain differential low noise amplifier (LNA) is designed for the impulse radio uitra-wideband (IR-UWB) system. The gain-flatten technique is adopted in this UWB LNA. Serial and shunt peaking techniques are used to achieve broadband input matching and large gain-bandwidth product (GBW). Feedback networks are introduced to further extend the bandwidth and diminish the gain fluctuations. The prototype is fabricated in the SMIC 0.18 μm RF CMOS process. Measurement results show a 3-dB gain bandwidth of 2.4-5.5 GHz with a maximum power gain of 13.2 dB. The excellent gain flatness is achieved with ±0.45 dB gain fluctuations across 3-5 GHz and the minimum noise figure (NF) is 3.2 dB over 2.5-5 GHz. This circuit also shows an excellent input matching characteristic with the measured S11 below-13 dB over 2.9-5.4 GHz. The input-referred 1-dB compression point (IPldB) is -11.7 dBm at 5 GHz. The differential circuit consumes 9.6 mA current from a supply of 1.8 V.     

5GHz0.18μm CMOS宽带LC VCO

采用0.18μm RF CMOS工艺,设计了一个5GHz的宽带电感电容压控振荡器。该压控振荡器的电路结构选用互补交叉耦合型,采用噪声滤波技术降低相位噪声,并采用开关电容阵列扩展其调谐范围。后仿真结果表明,实现了4.44～5.44GHz的宽调谐。振荡器的电源电压为1.8V,工作电流为2.78mA,版图面积为0.37mm2。     

0.18μm RF CMOS 3-5 GHz TH-UWB 通信射频发信机

本文给出一种3-5 GHz射频TH-UWB发信机的设计。该发信机由一个4GHz的振荡器,一个带衰减控制的MOS开关和一个输出匹配电路构成。由低速TH-PPM信号控制,该发信机输出中心频率为4GHz的TH-UWB信号,并能直接通过传输线驱动天线。采用0.18μm RF CMOS工艺实现,在1.8V电源下,输出信号峰值幅度在50Ω负载上为65mV。电路输出端口回波损耗S11小于-10dB。芯片占用面积为0.7 mm0.8 mm,功耗为12.3mW。     

A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18 μm CMOS for OFDM-UWB

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single (D2S) converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18/zm RF CMOS process with an area of 1.74 mm~2 and only consumes 32 mA current (at 1.8 V) including the test associated parts.     

0.18μm CMOS工艺5 GHz WLAN功率放大器设计

介绍采用TSMC公司的0.18μm CMOS工艺应用于5 GHzWLAN(无线局域网)发射集中的功率放大器的设计方法,并给出了仿真结果。电路采用A类三级放大结构,在3.3 V工作电压下,增益为23.7 dB,1 dB压缩点输出功率21.8 dBm,最大功率附加效率15%,可望用于WLAN 802.11a标准的系统中。     

A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

正A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm~2 and draws a total current of 221 mAfrom 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband /out-band IIP_3 better than-4 dBm/+9 dBm.The transmitter achieves an output power ranging from-10.7 to-3 dBm with gain control,an output P_(1dB) better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.     

A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm2 and draws a total current of 221 mA from 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/Step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband/out-band IIP3 better than-4 dBm/+9 dBm.The transmitter achieves an output power ranging from-10.7 to-3dBm with gain control,an output P1dB better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.     

A 5-GHz programmable frequency divider in 0.18-μm CMOS technology

正A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler(DMP) and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm;the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm~2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.     

A 2 GHz variable gain low noise amplifier in 0.18-μm CMOS

This paper describes a 2 GHz active variable gain low noise amplifier (VGLNA) in a 0.18-μm CMOS process. The VGLNA provides a 50-Ω input impedance and utilizes a tuned load to provide high selectivity. The VGLNA achieves a maximum small signal gain of 16.8 dB and a minimum gain of 4.6 dB with good input return loss. In the high gain and the low gain modes, the NFs are 0.83 dB and 2.8 dB, respectively. The VGLNA’s IIP3 in the high gain mode is 2.13 dBm. The LNA consumes approximately 4 mA of current from a 1.8-V power supply.     

7.3GHz 0.18μm CMOS注入式锁相环电路

给出一种利用0 .18μm CMOS工艺实现的注入式振荡器辅助锁相环.在1.8V电源电压下,电路工作频率为7.3GHz,功耗为15 7m W,跟踪范围为15 0 MHz,锁定时在1‰(7.3MHz)频率偏移量下的相位噪声为- 97.36 d Bc/Hz     

7.3GHz 0.18μm CMOS注入式锁相环电路

给出一种利用0.18μm CMOS工艺实现的注入式振荡器辅助锁相环.在1.8V电源电压下,电路工作频率为7.3GHz,功耗为157mW,跟踪范围为150MHz,锁定时在1‰(7.3MHz)频率偏移量下的相位噪声为-97.36dBc/Hz.     

A RF receiver frontend for SC-UWB in a 0.18-μm CMOS process

正A radio frequency(RF) receiver frontend for single-carrier ultra-wideband(SC-UWB) is presented. The front end employs direct-conversion architecture,and consists of a differential low noise amplifier(LNA),a quadrature mixer,and two intermediate frequency(IF) amplifiers.The proposed LNA employs source inductively degenerated topology.First,the expression of input impedance matching bandwidth in terms of gate-source capacitance, resonant frequency and target S_(11) is given.Then,a noise figure optimization strategy under gain and power constraints is proposed,with consideration of the integrated gate inductor,the bond-wire inductance,and its variation.The LNA utilizes two stages with different resonant frequencies to acquire flat gain over the 7.1-8.1 GHz frequency band,and has two gain modes to obtain a higher receiver dynamic range.The mixer uses a double balanced Gilbert structure.The front end is fabricated in a TSMC 0.18-/im RF CMOS process and occupies an area of 1.43 mm~2.In high and low gain modes,the measured maximum conversion gain are 42 dB and 22 dB,input 1 dB compression points are -40 dBm and -20 dBm,and S_(11) is better than -18 dB and -14.5 dB.The 3 dB IF bandwidth is more than 500 MHz.The double sideband noise figure is 4.7 dB in high gain mode.The total power consumption is 65 mW from a 1.8 V supply.     

A 0.18 μm CMOS 3-5 GHz broadband flat gain low noise amplifier

A 3-5 GHz broadband flat gain differential low noise amplifier(LNA) is designed for the impulse radio ultra-wideband(IR-UWB) system.The gain-flatten technique is adopted in this UWB LNA.Serial and shunt peaking techniques are used to achieve broadband input matching and large gain-bandwidth product(GBW).Feedback networks are introduced to further extend the bandwidth and diminish the gain fluctuations.The prototype is fabricated in the SMIC 0.18μm RF CMOS process.Measurement results show a 3-dB gain band...     

0.18μm CMOS 3.1-10.6GHz超宽带低噪声放大器设计

介绍了一种基于0.18μm CMOS工艺、适用于超宽带无线通信系统接收前端的低噪声放大器.在3.1～10.6GHz的频带范围内对它仿真获得如下结果:最高增益12dB;增益波动小于2dB;输入端口反射系数S11小于-10dB;输出端口反射系数S22小于-15dB;噪声系数NF小于4.6dB.采用1.5V电源供电,功耗为10.5mW.与近期公开发表的超宽带低噪声放大器仿真结果相比较,本电路结构具有工作带宽大、功耗低、输入匹配电路简单的优点.     

A 0.18μm CMOS fluorescent detector system for bio-sensing application

A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier （CTIA）, and a 12 bit pipelined analog-to- digital converter （ADC）, and is implemented in a 0.18μm standard CMOS process. Some special techniques, such as a ＂contact imaging＂ detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodiode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm^2 and consumes 37 mW.