基于Cadence界面的工艺设计包设计方法

详细阐述了基于Cadence界面的工艺设计包(PDK)的框架结构及设计方法;采用该方法,在Cadence界面上设计了一套实用的PDK库siscPDK;用实际的IC单元电路进行了验证,得到了正确的结果,证明了该方法的可行性.     

一种频率合成器的建模优化与电路设计

根据数模混合集成电路系统级和行为级快速验证的需求,设计了一种卫星导航系统射频接收机前端的频率合成器。传统行为级模型一般是基于理想环路进行参数提取,误差较大。为此,首先,分别利用MATLAB和Verilog-AMS对频率合成器建立理想行为级模型与非理想行为级模型,并根据行为级模型提取与优化的环路参数,采用SMIC 180 nm CMOS工艺设计仿真电路级频率合成器;其次,建立MATLAB噪声模型,对电路级各个模块的噪声进行拟合,评估频率合成器系统的整体噪声性能。所提出的频率合成器设计方法对电路级设计具有前瞻性的指导,并有助于电路级的设计优化。     

纳米集成电路 Cu CMP工艺模型参数优化

铜化学机械抛光受几何图形特性如线宽、间距和图形密度的影响,芯片和晶圆上铜互连线厚度的不均匀性都会影响电性能和降低良率。本文从物理化学的角度对CMP工艺进行了回顾和分析,针对Cu CMP制造工艺和在MIT提出的（Pattern-Density Step-Height,PDSH）模型基础上,建立与工艺相对应的三步骤工艺模型。为了扑捉工艺与版图结构的相关性,设计了一款65纳米测试芯片并在SMIC完成工艺实验。按照模型参数提取流程,通过芯片测试数据提取模型参数和验证工艺模型。模拟结果与测试结果对比说明二者趋势完全一致,最大偏差小于5 nm。第三方测试数据进一步证明模型参数优化取得很好的结果。精准的Cu CMP工艺模型可以用于做芯片的DFM检查、显示和消除关键热点,从而确保芯片的良率和集成电路量产能力。     

65nm工艺下百万门级芯片的物理设计

随着集成电路工艺的发展,集成电路后端物理设计变得越来越复杂,遇到了很多新的挑战。本文介绍了一款65nm工艺百万门级芯片的物理设计过程,论述了在布局规划、电源网络规划、时钟树设计、信号完整性、可制造性设计等方面的解决方案,提出了设计方法学上的改进,提高了后端物理设计效率和芯片的良率。     

A 10-bit low power SAR A/D converter based on 90 nm CMOS

Traditional and some recently reported low power, high speed and high resolution approaches for SAR A/D converters are discussed. Based on SMIC 65 nm CMOS technology, two typical low power methods reported in previous works are validated by circuit design and simulation. Design challenges and considerations for high speed SAR A/D converters are presented. Moreover, an R-C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process. The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively. With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively, and the power dissipation is measured to be just 3.17 mW.     

基于多项式基的Camellia算法S盒硬件优化

该文提出一种基于不可约多项式的Camellia算法S盒的代数表达式，并给出了该表达式8种不同的同构形式。然后，结合Camellia算法S盒的特点，基于理论证明给出一种基于多项式基的S盒优化方案，此方法省去了表达式中的部分线性操作。相对于同一种限定门的方案，在中芯国际(SMIC)130 nm工艺库中，该文方案减少了9.12%的电路面积；在SMIC 65 nm工艺库中，该文方案减少了8.31%的电路面积。最后，根据Camellia算法S盒设计中的计算冗余，给出了2类完全等价的有限域的表述形式，此等价形式将对Camellia算法S盒的优化产生积极影响。     

一种基于溢出值的局部拥塞消除技术

随着芯片的集成度越来越高,物理设计布局阶段的拥塞问题越发严重.提出了一种基于溢出值的局部拥塞消除技术,根据溢出值选择出拥塞密度最高的拥塞区域,然后基于模拟退火算法对该区域内的高引脚单元设置合适大小的隔离区域,以缓解局部拥塞.将提出的方法应用于SMIC 180 nm工艺的四万门设计和SMIC 55 nm工艺的七千门设计进...     

深亚微米下芯片后端物理设计方法学研究

随着摩尔定律的发展,90／65nm工艺下的大规模芯片越来越多,后端物理设计变得更加复杂,遇到了很多新问题,如高集成度、层次化设计、泄漏功耗、多角落-多模式、串扰噪声等,签收的标准也发生了变化。因此必须改进物理设计方法学,适应新的情况,来取得流片成功。     

Advanced CMOS technology portfolio for RF IC applications

A high quality 90-nm CMOS-based technology portfolio suitable for various RF IC applications is presented. The portfolio is built up by a wide selection of active and passive components and a user-friendly process design kit (PDK). Layout-optimized RF components are studied in details including state-of-the-art 90 nm RFMOS devices with 120-160 GHz f/sub T/ and very low noise figures, varactors with tradeoff between quality factor and tuning ratio, precision capacitors with metal-insulator-metal and metal-over-metal schemes, and a variety of inductor structures suitable for different RF designs. The effectiveness for isolating substrate RF noise is also compared among several layout schemes. Finally the guidelines and requirements for constructing a useful PDK are addressed.     

一种改进的40 Gb/s以太网循环冗余校验方法及电路设计

针对在40 Gb/s以太网规范中定义的循环冗余校验码(Cyclic Redundancy Code,CRC)计算关键路径过长的问题,提出了一种分块处理的方法来缩短每条关键路径的计算时间,从而满足时序的要求。对电路进行仿真,并使用中芯国际65 nm工艺库进行综合。验证结果表明,提出的分块并行计算方法正确,并且能够提高CRC计算速度,满足时序要求。     

一种新型低漏电ESD电源箝位电路

在到达纳米级工艺后,传统的静电放电防护(ESD)电源箝位电路的漏电对集成电路芯片的影响越来越严重。为降低漏电,设计了一种新型低漏电ESD电源箝位电路,该箝位电路通过2个最小尺寸的MOS管形成反馈来降低MOS电容两端的电压差。采用中芯国际40 nm CMOS工艺模型进行仿真,结果表明,在相同的条件下,该箝位电路的泄漏电流仅为32.59 nA,比传统箝位电路降低了2个数量级。在ESD脉冲下,该新型ESD箝位电路等效于传统电路,ESD器件有效开启。     

基于自偏置技术的低噪声锁相环研究

文中描述了一种自偏置型锁相环电路,通过采用环路自适应的方法得到一个固定的阻尼系数ξ以及带宽和输入频率的比值ωN/ωREF,从而保证环路的稳定。传统锁相环电路设计需要一个固定的电荷泵充放电电流和固定的VCO增益,这样才能保持系统的稳定性。但是当工艺发展到深亚微米尤其是65 nm以下的时候,芯片的供电电压都在1 V以下且器件的二级效应趋于严重,此时要得到一个固定的电流值或者固定的VCO增益是很困难的。自偏置锁相环解决了这个问题,由于采用了自适应环路的设计方法,使得系统受工艺、温度和电压的影响非常小,而且锁定范围更大。可以广泛应用于时钟发生器以及通信系统。芯片采用SMIC标准低漏电55 nm CMOS工艺制造,测试均方抖动为3.8 ps,峰-峰值抖动25 ps。     

Hardware design of motion data decoding process for H.264/AVC

In H.264/AVC, motion data can be basically derived by the following two schemes: one is a typical spatial prediction scheme based on the DPCM and the other is a sophisticated spatiotemporal prediction scheme for the skipped motion data, formally referred to as a direct mode. We verified through instruction level profiling that when these schemes are combined with various H.264/AVC coding techniques, the computational burden to derive the motion data could be considerably aggravated. Specifically, its computational complexity amounts to maximally 55% of that of the overall syntax parsing process. In this paper, we aim at an efficient hardware design of the motion data decoding process for H.264/AVC, for which all the key design considerations are addressed in detail and respective rational answers are presented. As comparing the resulting hardware design with the processor-based solution, its effectiveness was clearly demonstrated. The proposed design was implemented with 43.2 K logic gates and three on-chip memories of 3584 bits using Samsung Semiconductor’s Standard Cell Library in 65 nm L6LP process technology (SS65LP), and was capable of operating the H.264/AVC high-profile video bitstream of 1080p@60fps at 100 MHz consuming 843 μW.     

一个低功耗1G-samples/s,6-bit折叠插值ADC芯片设计

本文提出了一种具有高线性度的折叠,插值结构数模转换器(ADC)。与高速并行数模转换器(Flash ADC)相比较,该结构具有面积小,功耗低的特点,适用于低功耗超宽带(UWB)接收机中。本文对电路各部分进行了设计,并在SMIC 0.18μm工艺下完成了版图设计和后仿真。版图核心电路面积(不包括PAD)仅为0.45mm2,在1G samples/s采样率,输入信号为488.77MHz时,总功耗仅为57mW,有效位(ENOB)达到5.74bits。     

基于状态映射的AES算法硬件混淆设计

代码混淆利用系统自身逻辑来保护内部重要信息和关键算法,常用于软件代码的安全防护,确保开发者和用户的利益。如何在硬件电路上实现混淆、保护硬件IP核的知识产权,也是亟待解决的问题。该文通过对硬件混淆和AES算法的研究,提出一种基于状态映射的AES算法硬件混淆方案。该方案首先利用冗余和黑洞两种状态相结合的状态映射方式,实现有限状态机的混淆;然后,采用比特翻转的方法,实现组合逻辑电路的混淆;最后,在SMIC 65 nm CMOS工艺下设计基于状态映射的AES算法硬件混淆电路,并采用Toggle、数据相关性和代码覆盖率等评价硬件混淆的效率和有效性。实验结果表明,基于状态映射的AES算法硬件混淆电路面积和功耗分别增加9%和16%,代码覆盖率达到93%以上。     

一种基于自偏置技术的低抖动锁相环

设计了一种环路带宽与输入频率的比值固定的自偏置锁相环。对VCO延迟单元进行改进,降低了抖动。采用SMIC 65 nm CMOS工艺,在1.2 V的工作电压下对锁相环进行仿真,输出频率范围为0.5~3.125 GHz。仿真结果表明,在输出频率1.875 GHz处的峰峰值抖动为8.7 ps,电路的核心功耗为45 mW,相位噪声为-79.7 dBc/Hz。     

Embeded EEPROM Memory Achieving Lower Power - New design of EEPROM memory for RFID tag IC

A 2-kb embedded EEPROM memory, operating over a wide voltage range (typically 2.5 V-5 V), was designed and fabricated using the SMIC 0.35-mum 2P3M CMOS embedded EEPROM process. The chip size is about 0.6 mm². The method of adding control transistors improved the static power dissipation. The transient power consumption of the charge pump circuit was greatly reduced by using a slowly varying clock. The proposed SA using a voltage sensing method also significantly improved the read power dissipation. By employing these techniques, a low-power embedded EEPROM memory with 40 muA read current and 250 muA page write current was developed, that achieved much lower power than EEPROM memory designs reported in scientific journals or conferences. This EEPROM memory was used in the ISO/IEC 15693-compatible RFID tag IC project     

Design of replica bit line control circuit to optimize power for SRAM

A design of a replica bit line control circuit to optimize power for SRAM is proposed. The proposed design overcomes the limitations of the traditional replica bit line control circuit, which cannot shut off the word line in time. In the novel design, the delay of word line enable and disable paths are balanced. Thus, the word line can be opened and shut off in time. Moreover, the chip select signal is decomposed, which prevents feedback oscillations caused by the replica bit line and the replica word line. As a result, the switch power caused by unnecessary discharging of the bit line is reduced. A 2-kb SRAM is fully custom designed in an SMIC 65-nm CMOS process. The traditional replica bit line control circuit and the new replica bit line control circuit are used in the designed SRAM, and their performances are compared with each other. The experimental results show that at a supply voltage of 1.2 V, the switch power consumption of the memory array can be reduced by 53.7%.