共查询到20条相似文献,搜索用时 46 毫秒
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Wei Jin Weidong Liu Fung S.K.H. Chan P.C.H. Chenming Hu 《Electron Devices, IEEE Transactions on》2001,48(4):730-736
The buried-oxide in SOI MOSFET inhibits heat dissipation in the Si film and leads to increase in transistor temperature. This paper reports a simple and accurate characterization method for the self-heating effect (SHE) in SOI MOSFETs. The AC output conductance at a chosen bias point is measured at several frequencies to determine the thermal resistance (Rth) and thermal capacitance (Cth) associated with the SOI device. This methodology is important to remove the misleadingly large self-heating effect from the DC I-V data in device modeling. Not correcting for SHE may lead to significant error in circuit simulation. After SHE is accounted for, the frequency-dependent SHE may be disabled in circuit simulation without sacrificing the accuracy, thus providing faster circuit simulation for high-frequency circuits 相似文献
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Fiegna C. Yang Yang Sangiorgi E. O'Neill A.G. 《Electron Devices, IEEE Transactions on》2008,55(1):233-244
This paper discusses self-heating (SHE) effects in silicon-on-insulator (SOI) CMOS technology and applies device simulation to analyze the impact of thermal effects on the operation of nanoscale SOI n-MOSFETs. A 2-D drift-diffusion electrothermal simulation, using an electron transport model calibrated against Monte Carlo simulations at various temperatures, is employed in the analysis. We report the effects of device-structure parameters, such as SOI layer thickness, buried-oxide (BOX) thickness, source/drain (S/D) extension length, and thickness of the elevated S/D region, on the SHE of nanoscale MOSFETs. The SHE effects become significant due to the adoption of thin silicon layers and to the low thermal conductivity of the BOX, leading to the rise of large temperature under nominal operation conditions for high-performance digital circuits. The ac performance of SOI MOSFETs is influenced as well, and in particular, a severe degradation of the cutoff frequency of very short MOSFETs is predicted by numerical electrothermal device simulations. Although the effects of SHE on device performance are found to be somewhat modest and might be mitigated through device design, they may result in a degradation of the long-term reliability. 相似文献
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TONGJian-nong ZOUXue-cheng SHENXu-bang 《半导体光子学与技术》2004,10(2):127-132
A numerical schemes applicable to the direct solution of Boltzmann transport equation (BTE) in vertical-SOI NMOSFET are investigated by means of the finite element analysis (FEA). The solution gives the electron distribution function, electrostatic potential, carriers concentration, drift velocity, average energy and drain current by directly solving the BTE and the Poisson equation self-consistency. The result shows that the direct numerical solution of the BTE with the aid of FEA and vertical SOI NMOSFET is a promising approach for ultra short channel transistors modeling. 相似文献
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A physics-based thermal circuit model is developed for electro-thermal simulation of SOI analog circuits. The circuit model integrates a non-isothermal device thermal circuit with interconnect thermal networks and is validated with high accuracy against finite element simulations in different layout structures. The non-isothermal circuit model is implemented in BSIMSOI to account for self-heating effect (SHE) in a Spice simulator, and applied to electro-thermal simulation of an SOI cascode current mirror constructed using different layouts. Effects of layout design on electric and thermal behaviors are investigated in detail. Influences of BOX thickness are also examined. It has been shown that the proposed non-isothermal approach is able to effectively account for influences of layout design, self-heating, high temperature gradients along the islands, interconnect temperature distributions, thermal coupling, and heat losses via BOX and interconnects, etc., in SOI current mirror structures. The model provides basic concepts and thermal circuits that can be extended to develop an effective model for electro-thermal simulation of SOI analog ICs. 相似文献
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SiGe沟道SOI CMOS的设计及模拟 总被引:1,自引:0,他引:1
在 SOI(Silicon on Insulator)结构硅膜上面生长一层 Si Ge合金 ,采用类似 SOICMOS工艺制作成具有Si Ge沟道的 SOICMOS集成电路。该电路不仅具有 SOICMOS电路的优点 ,而且因为 Si Ge中的载流子迁移率明显高于 Si中载流子的迁移率 ,所以提高了电路的速度和驱动能力。另外由于两种极性的 SOI MOSFET都采用 Si Ge沟道 ,就避免了只有 SOIPMOSFET采用 Si Ge沟道带来的选择性生长 Si Ge层的麻烦。采用二维工艺模拟得到了器件的结构 ,并以此结构参数进行了器件模拟。模拟结果表明 ,N沟和 P沟两种 MOSFET的驱动电流都有所增加 ,PMOSFET增加得更多一些 相似文献
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Fully depleted (FD) silicon-on-insulator (SOI) MOSFET structure with back-gate bias is suggested for high speed and low power consumption for portable communication application. Ni silicide is demonstrated for improving current drivability for low power consumption by reducing series resistance in the source and drain region. Threshold voltage adjustment is also achieved through applied back-gate bias. For the formation of the buried back-gate, the selection of impurity type as well as its doping concentration is controlled. Employing back-gate bias for FD-SOI NMOSFET, improved current drivability with variable threshold voltage is achieved. Short channel devices are fabricated and its electrical characteristics are obtained under various conditions. 相似文献
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Self-heating characterization and extraction method for thermal resistance and capacitance in HV MOSFETs 总被引:1,自引:0,他引:1
This letter reports on the self-heating effect (SHE) characterization of high-voltage (HV) DMOSFETs and the accurate extraction of the equivalent thermal impedance of the device (thermal resistance, R/sub TH/, and capacitance, C/sub TH/) needed for advanced device and IC simulation. A simple pulsed-gate experiment is proposed and the influence of its parameters (pulse duration and duty factor) are analyzed. It is demonstrated that in our 100 V DMOSFET, SHE is cancelled by using pulses with duration less that 2 /spl mu/s and duty factor lower that 1:100. The new extraction method exploits analytical modeling and dedicated extraction plots for thermal resistance and capacitance using the measurements of output characteristics at various applied pulses and the gradual reduction of SHE with pulse duration and duty factor. Both R/sub TH/ and C/sub TH/ are extracted in saturation region considering their dependence on SHE and external temperature. In DMOSFETs, the thermal resistance is shown to be a significant linear function of the device temperature (in our device, R/sub TH/ could increase by more than 100% over 100/spl deg/C). The thermal capacitance appears to decrease with the injected power and shows a plateau at high V/sub D/. SPICE simulations with the extracted thermal network R/sub TH/-C/sub TH/ circuit are finally used to fully validate the proposed method. 相似文献
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We propose a novel power metal oxide semiconductor field effect transistor (MOSFET) employing a strained‐Si channel structure to improve the current drivability and on‐resistance characteristic of the high‐voltage MOSFET. A 20 nm thick strained‐Si low field channel NMOSFET with a 0.75 µm thick Si0.8Ge0.2 buffer layer improved the drive current by 20% with a 25% reduction in on‐resistance compared with a conventional Si channel high‐voltage NMOSFET, while suppressing the breakdown voltage and subthreshold slope characteristic degradation by 6% and 8%, respectively. Also, the strained‐Si high‐voltage NMOSFET improved the transconductance by 28% and 52% at the linear and saturation regimes. 相似文献
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Jong-Ho Lee Hyung-Cheol Shin Jong-June Kim Choon-Bae Park Young-June Park 《Electron Device Letters, IEEE》1997,18(5):184-186
A new SOI NMOSFET with a “LOCOS-like” shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, we developed a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3 μm SOI devices with Vz of 0.773 V and Tox=7.6 nm is 360 μA/μm at VGS=3.5 V and V DS=2.5 V. Improved breakdown characteristics were obtained and the BVDSS (the drain voltage for 1 nA/μm of ID at TGS=0 V) of the device with Leff=0.3 μm under the floating body condition was as high as 3.7 V 相似文献
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Mansun Chan Yuen S.S. Zhi-Jian Ma Hui K.Y. Ko P.K. Chenming Hu 《Electron Devices, IEEE Transactions on》1995,42(10):1816-1821
The electrostatic discharge (ESD) protection capability of SOI CMOS output buffers has been studied with Human Body Model (HBM) stresses. Experimental results show that the ESD voltage sustained by SOI CMOS buffers is only about half the voltage sustained by the bulk NMOS buffers. ESD discharge current in a SOI CMOS buffer is found to be absorbed by the NMOSFET alone. Also, SOI circuits display more serious reliability problem in handling negative ESD discharge current during bi-directional stresses. Most of the methods developed for bulk technology to improve ESD performance have minimal effects on SOI. A new Through Oxide Buffer ESD protection scheme is proposed as an alternative for SOI ESD protection. In order to improve ESD reliability, ESD protection circuitries can be fabricated on the SOI substrate instead of the top silicon thin film, after selectively etching through the buried oxide. This scheme also allows ESD protection strategies developed for bulk technology to be directly transferred to SOI substrate.<> 相似文献
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超深亚微米部分耗尽SOI NMOSFET关态应力下前栅和背栅晶体管损伤研究 总被引:1,自引:1,他引:0
The hot-carrier effect charactenstic in a deep submicron partially depleted SOI NMOSFET is investigated. Obvious hot-carrier degradation is observed under off-state stress.The hot-carrier damage is supposed to be induced by the parasitic bipolar effects of a float SOI device.The back channel also suffers degradation from the hot carrier in the drain depletion region as well as the front channel.At low gate voltage,there is a hump in the sub-threshold curve of the back gate transistor,and it does not shift in the same way as the main transistor under stress.While under the same condition,there is a more severe hot-carrier effect with a shorter channel transistor. The reasons for those phenomena are discussed in detail. 相似文献
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0.5μm部分耗尽SOI MOSFET的寄生双极效应严重影响了SOI器件和电路的抗单粒子和抗瞬态γ辐射能力。文中显示,影响0.5μm部分耗尽SOI NMOSFET寄生的双极器件特性的因素很多,包括NMOSFET的栅上电压、漏端电压和体接触等,尤其以体接触最为关键。在器件处于浮体状态时,0.5μm SOI NMOSFET的寄生双极器件很容易被触发,导致单管闭锁。因此,在设计抗辐射SOI电路时,需要尽量降低SOI NMOSFET寄生双极效应,以提高电路的抗单粒子和抗瞬态γ辐射能力。 相似文献
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Mohammad K. Anvarifard 《International Journal of Electronics》2013,100(8):1394-1406
A novel structure such as nanoscale silicon-on-insulator (SOI) MOSFET with silicon embedded layer (SEL-SOI) is proposed to reduce self-heating effects (SHEs) successfully. The SEL as a useful heat sink with high thermal conductivity is inserted inside the buried oxide. The SEL acts like a heat sink and is therefore easily able to distribute the lattice heat throughout the device. We noticed excellent improvement in the thermal performance of the device using two-dimensional and two-carrier device simulation. Our simulation results show that SHE has been dramatically reduced in the proposed structure. In regard to the simulated results, the SEL-SOI structure has shown good performance in comparison with the conventional SOI (C-SOI) structure when utilised in the high temperature applications. 相似文献
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Using the hybrid nonlinear finite element method (FEM), electrothermomechanical analysis of partially insulated field-effect transistors (PiFETs) is performed in this paper, with their temperature-dependent material parameters treated rigorously. Two types of PiFETs, namely partially insulating oxides (PiOX) under the drain/source (PUSD) and channel (PUC), are studied and compared. The impact of self-heating effect (SHE) on their I-V characteristic, current degradation, temperature and thermal stress distribution are investigated, with some comparisons also made among normal MOSFET, PUSD PiFET, PUC PiFET and SOI FET. The influences of PiOX length, PiOX thickness, and electrode material on their maximum temperature and thermal stress are predicted, which can provide some pragmatic criterion for the development of PiFETs with good reliability. 相似文献
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From a two-dimensional solution of Laplace's equation it is shown that a significant increase in temperature occurs in the channel of SOI transistors due to the relatively poor thermal conductivity of the buried insulator. Based on this simulation an equation is derived which predicts that at small channel lengths the pinchoff point is shifted, an effect which is consistent with experimental observations. In addition, the positive 'kink' is reduced with the negative differential resistance, can be explained by a temperature increase in the channel.<> 相似文献