一个没有采用校准技术的12位分辨率100兆采样率的流水线模数转换器

本文给出了一个基于0.18um CMOS工艺的12bit 100MS/s的流水线ADC。其中第一级采用了3.5比特结构以降低对电容匹配的要求,采样保持放大器、第一级和第二级均采用了自举开关以改善ADC线性度,后级采用级缩减技术节省了功耗和面积。当输入信号频率为15.5MHz、采样率为100MHz时,该ADC达到了79.8dB的SFDR和10.5bit的有效位数。芯片采用1.8V电压供电,包含输出驱动的总功耗为112mW, 芯片面积为3.51mm2 。     

A 12-bit 100 MS/s pipelined ADC with digital background calibration

This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC) with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter (MDAC) while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3×1.6 mm~2, and consumes 205 mW at 1.8 V.     

采用后台数字校准的12位100MHz流水线模数转换器

This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter （MDAC） while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3 × 1.6 mm^2, and consumes 205 mW at 1.8 V.     

一种8位100 MS/s的低功耗流水线型ADC

基于0.35 μm CMOS工艺,设计并制作了一种低功耗流水线型ADC。分析了ADC结构对功耗的影响,采用1.5位/级的流水线结构来最小化功耗,并提升速度。为进一步降低功耗,设计了一种不带补偿并可调节相位裕度的共源共栅跨导放大器(OTA)和改进的比较器。测试结果显示,该ADC在3 V电源电压、100 MS/s采样速率下,功耗为65 mW,面积为0.73 mm²,在模拟输入频率为70.1 MHz和141 MHz下的无杂散动态范围(SFDR)分别为59.8 dBc和56.5 dBc。该ADC可应用于需要欠采样的通信系统中。     

14-bit 100 MS/s 121 mW pipelined ADC

本文实现了一款低功耗、小面积的高速高精度流水线型模数转换器,可以作为IP核应用于片上系统中。该模数转换器应用了逐级尺寸递减、运放共享等技术来实现低功耗的设计。采用分离的双输入通道共享的运算放大器输入端,从而实现运放共享带来的级间串扰、记忆效应等非线性影响的消除。同时,该模数转换器中采用了动态预放大比较器的设计来减小比较器的静态功耗以及回踢噪声的影响。本设计在SMIC 0.18μm CMOS工艺下流片,实现面积开销为3.1mm2。在采样频率为100MHz,输入信号为2.4MHz的情况下,实现无杂散动态范围（SFDR）为82.7dB,信号噪声失真比（SNDR）为69.1dB。在输入信道达到100MHz的情况下,实现SFDR和SNDR分别为81.4dB和65.8dB。该模数转换器的供电电压为1.8V,功耗开销为121mW。     

一种采用开关内置双输入MDAC的10b 80 MS/s 运放共享流水线模数转换器

在0.18-μm CMOS工艺下设计了一种10位80MHz采样频率的运放共享流水线模数转换器,提出了一种开关内置的双输入运放共享的MDAC,从而有效的消除了传统结构存在的无法复位和级间干扰通路的问题。测试结果显示,本设计的模数转换器的SNDR可以达到60.1dB,无杂散动态范围可以达到76dB,有效位为9.69 bit,在整个奈奎斯特带宽内有效位均高于9.6bit。芯片核心面积为1.1 mm2,在1.8 V电源电压下功耗为28mW。     

一种带校准的1.8V 1.1MS/s 96.1dB-SFDR的逐次逼近模数转换器

A power efficient 96.1 dB-SFDR successive approximation register(SAR) analog-to-digital converter (ADC) with digital calibration aimed at capacitor mismatch is presented.The prototype is fabricated in a 0.18μm CMOS.The charge redistribution(CR) design and an extra△∑modulator for capacitance measurement are employed. With a 1.1 MS/s sampling rate,the ADC achieves 70.8 dB SNDR and the power consumption is 2.1 mW.     

A 10-bit 80-MS/s opamp-sharing pipelined ADC with a switch-embedded dual-input MDAC

A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18-μm CMOS.An opampsharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique.The ADC achieves a peak SNDR of 60.1 dB(ENOB = 9.69 bits) and a peak SFDR of 76 dB,while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth.The core area of the ADC is 1.1 mm~2 and the chip consumes 28 mW with a 1.8 V power supply.     

一个电容阵列定制的100MS/s，9bit，0.43mW逐次逼近型模数转换器

本论文介绍了一个带定制电容阵列的低功耗9bit,100MS/s逐次比较型模数转换器。其电容阵列的基本电容单元是一个新型3D,电容值为1fF的MOM电容。除此之外,改进后的电容阵列结构和开关转换方式也降低了不少功耗。为了验证设计的有效性,该比较器在TSMC IP9M 65nm LP CMOS工艺下流片。测试结果如下：采样频率100MS/s,输入频率1MS/s时,有效位数（ENOB）为7.4,bit,信噪失真比（SNDR）为46.40dB,无杂散动态范围（SFDR）为62.31dB。整个芯片核面积为0.030mm2,在1.2V电源电压下功耗为0.43mW。该设计的品质因数（FOM）为23.75fJ/conv。     

一种不带校正SFDR为85.2dB的14位100兆流水线模数转换器

This paper describes a 14-bit 100-MS/s calibration-free pipelined analog-to-digital converter （ADC）. Choices for stage resolution as well as circuit topology are carefully considered to obtain high linearity without any calibration algorithm. An adjusted timing diagram with an additional clock phase is proposed to give residue voltage more settling time and minimize its distortion. The ADC employs an LVDS clock input buffer with low-jitter consideration to ensure good performance at high sampling rate. Implemented in a 0.18-μm CMOS technology, the ADC prototype achieves a spurious free dynamic range （SFDR） of 85.2 dB and signal-to-noise-and-distortion ratio （SNDR） of 63.4 dB with a 19.1-MHz input signal, while consuming 412-mW power at 2.0-V supply and occupying an area of 2.9 × 3.7 mm^2.     

一种数字CMOS工艺制造的10位100MS/s流水线ADC

介绍了采用0.18μm数字工艺制造、工作在3.3V下、10位100MS/s转换速率的流水线模数转换器。提出了一种适用于1.5位MDAC的新的金属电容结构,并且使用了高带宽低功耗运算放大器、对称自举开关和体切换的PMOS开关来提高电路性能。芯片已经通过流片验证,版图面积为1.35mm×0.99mm,功耗为175mW。14.7MS/s转换速率下测得的DNL和INL分别为0.2LSB和0.45LSB,100MS/s转换速率下测得的DNL和INL分别为1LSB和2.7LSB,SINAD为49.4dB,SFDR为66.8dB。     

一种10位100-MS/s CMOS流水折叠式A/D转换器

采用流水折叠结构设计了一种10位100-MSample/s A/D转换器。失调取消技术和电阻平均插值网络提高了转换器的线性度。级联结构放宽了折叠放大器的带宽要求,采用分布式级间跟踪保持放大器实现流水线技术来获得更高的转换精度。基于SMIC 0.18 μm CMOS工艺的测试结果如下：INL和DNL的峰值分别为0.48 LSB and 0.33 LSB。输入电压范围VP-P为1.0 V,芯片面积2.29 mm2。100 MHz采样,20 MHz输入信号下,ENOB为9.59位,SNDR为59.5 dB,SFDR为82.49 dB。1.8V电源电压下功耗仅为95 mW。     

一种采用改进放大器的12位40兆采样率的流水线模数转换器

本文设计实现了一种采用改进放大器的12位40兆采样率的流水线模数转换器。基于该模数转换器的结构,本文分析了影响模数转换器的精度的放大器非理想因素,并提出了针对放大器的补偿技术。该技术消除了增益提高技术和开关电容共模反馈结构对放大器的带宽和相位裕度的限制。整个模数转换器使用0.35μm标准CMOS工艺设计制作。测试结果表明,该模数转换器能够在2V输入范围内,40兆赫兹采样时钟下实现60.5dB信噪失真比和74.5dB的无杂散动态范围。     

A 12-bit,40-Ms/s pipelined ADC with an improved operational amplifier

This paper proposes a 12-bit,40-Ms/s pipelined analog-to-digital converter(ADC) with an improved high-gain and wide-bandwidth operational amplifier(opamp).Based on the architecture of the proposed ADC,the non-ideal factors of opamps are first analyzed,which have the significant impact on the ADC's resolution.Then,the compensation techniques of the ADC's opamp are presented to restrain the negative effect introduced by the gainboosting technique and switched-capacitor common-mode-feedback structure.After analysis and optimization,the ADC implemented in a 0.35μm standard CMOS process shows a maximum signal-to-noise distortion ratio of 60.5 dB and a spurious-free dynamic range of 74.5 dB,respectively,at a 40 MHz sample clock with over 2 Vpp input range.     

一种有效位为11.3比特的14位100兆CMOS流水线型模数转换器

This paper demonstrates a 14-bit 100-MS/s pipelined analog-to-digital converter(ADC) in 0.18μm CMOS process with a 1.8 V supply voltage.A fast foreground digital calibration mechanism is employed to correct capacitor mismatches.The ADC implements an SHA-less 3-bit front-end to reduce the size of the sampled capacitor. The presented ADC achieves a 70.02 dB signal-to-noise distortion ratio(SNDR) and an 87.5 dB spurious-free dynamic range(SFDR) with a 30.7 MHz input signal,while maintaining over 66 dB SNDR and 76 dB SFDR up to 200 MHz input.The power consumption is 543 mW and a total die area of 3 x 4 mm2 is occupied.     

一种16.9 mW 10 bit 50 Msample/s 流水线ADC IP核设计

设计了一个10位50 Msample/s流水线ADC IP核.采用SMIC 0.25 μm 1P5M数字CMOS工艺,通过使用运算放大器共享技术、电容逐级缩减技术和对单元电路的优化,使得整个IP核面积仅为0.24 mm2.仿真结果表明,在50 MHz采样率、输入信号为2.04 MHz正弦信号情况下,该ADC模块具有8.9 bit的有效分辨率,最大微分非线性为0.65 LSB,最大积分非线性为1.25 LSB,而整个模块的功耗仅为16.9 mW.     

A 10-bit 100-MS/s CMOS pipelined folding A/D converter

This paper presents a 10-bit 100-MSample/s analog-to-digital（A/D） converter with pipelined folding architecture.The linearity is improved by using an offset cancellation technique and a resistive averaging interpolation network.Cascading alleviates the wide bandwidth requirement of the folding amplifier and distributed interstage track/hold amplifiers are used to realize the pipeline technique for obtaining high resolution.In SMIC 0.18μm CMOS,the A/D converter is measured as follows:the peak integral nonlinearity and differential nonlinearity are±0.48 LSB and±0.33 LSB,respectively.Input range is 1.0 V_P-P with a 2.29 mm² active area.At 20 MHz input @ 100 MHz sample clock,9.59 effective number of bits,59.5 dB of the signal-to-noise-and-distortion ratio and 82.49 dB of the spurious-free dynamic range are achieved.The dissipation power is only 95 mW with a 1.8 V power supply.     

14位100MSPS流水线ADC的低功耗设计

为实现14位100MSPS流水线模数转换器(ADC)的低功耗设计,提出了一种新型的运放和电容共享技术。该技术将流水线ADC的前端采样保持电路(SHC)并入第一流水线级,并在后面的流水线级中相邻两级使用运放共享技术,消除了常规的运放和电容共享技术所存在的需要额外置零状态和引入的额外开关影响运放建立时间的缺点。芯片采用TSMC 0.18μm互补型金属氧化物半导体(CMOS)混合信号工艺,仿真结果表明,在100MSPS采样率和10MHz输入信号频率下,ADC可达到77.6dB的信号噪声失调比(SNDR),87.3dB的无杂散动态范围(SFDR),±0.4LSB的微分非线性(DNL),±1LSB的积分非线性(INL),0.56pJ/conv的品质因数(FOM),在3.3V供电情况下功耗为350mW。     

一种SFDR为83.5dB的14位100兆流水线模数转换器

This paper demonstrates a 14-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC）. The nonlinearity model for bootstrapped switches is established to optimize the design parameters of bootstrapped switches, and the calculations based on this model agree well with the measurement results. In order to achieve high linearity, a gradient-mismatch cancelling technique is proposed, which eliminates the first order gradient error of sampling capacitors by combining arrangement of reference control signals and capacitor layout. Fabricated in a 0.18-μm CMOS technology, this ADC occupies 10.16-mm2 area. With statistics-based background calibration of finite opamp gain in the first stage, the ADC achieves 83.5-dB spurious free dynamic range and 63.7-dB signalto-noise-and distortion ratio respectively, and consumes 393 mW power with a supply voltage of 2 V.