10bit 100M低功耗时间交织运放共享模数转换器设计

本文设计了一个应用于3G接收机中频的10比特100兆采样率的双通道时间交织流水线模数转换器,为了降低功耗,运放在两通道间共享。针对通道间的直流失调失配,增益失配以及采样时间偏差,设计分别采用共享运放,增加每个通道转换精度以及全局采样技术来加以解决。通过改变时序,消除了输出开关电荷注入以及断开开关的电容造成的串扰,从而提高了整个模数转换器的线性度。整个模数转换器的供电电压为3.3V,功耗为70毫瓦,采用了180纳米CMOS工艺,面积为3×2mm2,在奈奎斯特频率以内,其杂散无失真动态范围大于70dB,其信杂比大于56dB。     

适用于中频采样的低功耗时间交织10位250Msps电荷域流水线ADC

A 10-bit 250-MSPS two-channel time-interleaved charge-domain(CD) pipelined analog-to-digital converter (ADC) is presented.MOS bucket-brigade device(BBD) based CD pipelined architecture is used to achieve low power consumption.An all digital low power DLL is used to alleviate the timing mismatches and to reduce the aperture jitter.A new bootstrapped MOS switch is designed in the sample and hold circuit to enhance the IF sampling capability.The ADC achieves a spurious free dynamic range(SFDR) of 67.1 dB,signal-to-noise ratio (SNDR) of 55.1 dB for a 10.1 MHz input,and SFDR of 61.6 dB,SNDR of 52.6 dB for a 355 MHz input at full sampling rate.Differential nonlinearity(DNL) is +0.5/-0.4 LSB and integral nonlineariry(INL) is +0.8/-0.75 LSB.Fabricated in a 0.18-μm 1P6M CMOS process,the prototype 10-bit pipelined ADC occupies 1.8×1.3 mm2 of active die area,and consumes only 68 mW at 1.8 V supply.     

14位100MSPS流水线ADC的低功耗设计

为实现14位100MSPS流水线模数转换器(ADC)的低功耗设计,提出了一种新型的运放和电容共享技术。该技术将流水线ADC的前端采样保持电路(SHC)并入第一流水线级,并在后面的流水线级中相邻两级使用运放共享技术,消除了常规的运放和电容共享技术所存在的需要额外置零状态和引入的额外开关影响运放建立时间的缺点。芯片采用TSMC 0.18μm互补型金属氧化物半导体(CMOS)混合信号工艺,仿真结果表明,在100MSPS采样率和10MHz输入信号频率下,ADC可达到77.6dB的信号噪声失调比(SNDR),87.3dB的无杂散动态范围(SFDR),±0.4LSB的微分非线性(DNL),±1LSB的积分非线性(INL),0.56pJ/conv的品质因数(FOM),在3.3V供电情况下功耗为350mW。     

14-bit 100 MS/s 121 mW pipelined ADC

本文实现了一款低功耗、小面积的高速高精度流水线型模数转换器,可以作为IP核应用于片上系统中。该模数转换器应用了逐级尺寸递减、运放共享等技术来实现低功耗的设计。采用分离的双输入通道共享的运算放大器输入端,从而实现运放共享带来的级间串扰、记忆效应等非线性影响的消除。同时,该模数转换器中采用了动态预放大比较器的设计来减小比较器的静态功耗以及回踢噪声的影响。本设计在SMIC 0.18μm CMOS工艺下流片,实现面积开销为3.1mm2。在采样频率为100MHz,输入信号为2.4MHz的情况下,实现无杂散动态范围（SFDR）为82.7dB,信号噪声失真比（SNDR）为69.1dB。在输入信道达到100MHz的情况下,实现SFDR和SNDR分别为81.4dB和65.8dB。该模数转换器的供电电压为1.8V,功耗开销为121mW。     

低功耗12b 40M流水线模数转换器

本文介绍了一个12b 40M流水线模数转换器（ADC）,在0.18um CMOS工艺下流片,工作电压3.3V,功耗76mW。为了实现功耗优化,流水线各级采用了多比特结构和套筒式运算放大器。模数转换器的前两级采用3比特/级结构,以提高转换器线性度。该模数转换器不需要校正,经测试DNL小于0.51-LSB,INL小于1LSB。当模数转换器工作在40MHz采样率时,在奈奎斯特频率以内,SNDR指标大于67dB;在49MHz以内的输入信号频带内,SFDR指标在80dB左右,变化幅度不超过1-dB。     

A low power 12-b 40-MS/s pipeline ADC

This paper describes a 12-bit, 40-MS/s pipelined A/D converter (ADC) which is implemented in 0.18-μm CMOS process drawing 76-mW power from 3.3-V supply. Multi-bit architectures as well as telescopic operational transconductance amplifiers (OTAs) are adopted in all pipeline stages for good power efficiency. In the first two stages,particularly, 3-bit/stage architectures are used to improve the ADC's linearity performance. The ADC is calibration-free and achieves a DNL of less than 0.51 LSB and an INL of less than 1 LSB. The SNDR performance is above 67 dB below Nyquist. The 80-dB SFDR performance is maintained within 1 dB for input frequencies up to 49 MHz at full sampling rate.     

一种采用Replica控制PVT波动不敏感电荷传输电路的10位250MSPS电荷域流水线模数转换器

本文提供了一种低功耗电荷域10位250Msps电荷域流水线模数转换器（ADC）。通过采用基于BBD的电荷域流水线技术实现,使得ADC具有超低功耗;通过采用一种Replica控制PVT波动不敏感BCT电路,在不降低电荷传输速度的条件下抑制了PVT波动敏感性。采用0.18um CMOS工艺,在没有采用共模控制和误差校准技术的条件下,所实现的10位电荷域ADC在250MHz全速采样时对于9.9MHz正弦输入信号转换得到的无杂散动态范围（SFDR）为64.74dB,信噪失真比（SNDR）为56.9dB,有效位数（ENOB）达9.1比特,最大微分线性度（DNL）为 0.5/-0.5 LSB,最大积分线性度（INL）为 0.8/-0.85 LSB,并且在1.8V电源条件下整个电路功耗仅为45mW,整个ADC有源芯片面积为1.2×1.3 mm2。     

一种10位高速Pipeline-SAR混合型ADC设计

基于180 nm CMOS工艺,设计了一种无残差放大的10位100 MS/s流水线与逐次逼近混合型ADC。采用两级流水线-逐次逼近混合型结构,第一级完成4位粗量化转换,第二级完成6位细量化转换。为了降低整体电路功耗,采用单调式电容控制切换方式,两级之间残差电压采用采样开关电荷共享方式实现。采用异步时序控制逻辑,进一步提升了能量利用率和转换速度。后仿真结果表明,在100 MS/s奈奎斯特采样率下,有效位数为9.39 bit,信噪失真比为58.34 dB,1.8 V电源电压下整体功耗为5.9 mW。     

一种采用PVT不敏感电荷传输电路的27mW 10位125MSPS 电荷域流水线模数转换器

A low power 10-bit 125-MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) based on MOS bucket-brigade devices(BBDs) is presented.A PVT insensitive boosted charge transfer(BCT) that is able to reject the charge error induced by PVT variations is proposed.With the proposed BCT,the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced remarkably.The prototype ADC based on the proposed BCT is realized in a 0.18μm CMOS process,with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm~2.The prototype ADC achieves a spurious free dynamic range(SFDR) of 67.7 dB,a signal-to-noise ratio(SNDR) of 57.3 dB,and an effective number of bits(ENOB) of 9.0 for a 3.79 MHz input at full sampling rate.The measured differential nonlinearity(DNL) and integral nonlinearity (INL) are +0.5/-0.3 LSB and +0.7/-0.55 LSB,respectively.     

一种低功耗11位100MS/s采样率SAR ADC IP

本文介绍了一种双通道11位100MS/s采样率的混合结构SAR ADC IP。每个通道均采用flash-SAR结构以达到高速低功耗的目的。为了进一步降低功耗,flash和SAR中的比较器均采用全动态比较器。SAR中逐次逼近逻辑所需要的高速异步触发时钟采用门控环形振荡器产生。为了提高电容的匹配性,在版图设计中,采用底板包围顶板的MOM电容结构,有效减小电容寄生。本设计制造工艺为SMIC55nm的低漏电CMOS工艺,双通道的总面积为0.35mm2且核心面积仅为0.046 mm2。双通道模数转换器在1.2V供电电压下消耗的总电流为2.92mA。在2.4MHz输入和50MHz输入下的有效转换位数（ENOB）分别为9.9位和9.34位。计算得出本设计的FOM值为18.3fJ/conversion-step。     

采用双采样结构和Class-AB OTA的低功耗14bit，51.2KS/s扩展计数型ADC设计

本文设计并实现了一种14bit,51.2KS/S扩展计数型模数变换器(ADC)。该ADC采用两种技术来降低电路的功耗。首先,提出了一种基于全浮空双线性(fully-floating bilinear)积分器的双采样结构,并利用这种结构降低时钟频率。其次,采用了AB类运算跨导放大器(OTA)来提高电路的功耗效率。另外,该ADC还采用了斩波技术消除1/f噪声的影响。该ADC结构采用0.18μm CMOS工艺进行了实现,单个ADC的面积仅为0.04mm2。其转换速率为51.2KS/s,测试所得无杂散动态范围(SFDR)为94dB,有效位数(ENOB)为11.6位,电源电压为1.8V,功耗为77μW。该ADC的优值仅为0.48pJ/step。     

一个低功耗1G-samples/s,6-bit折叠插值ADC芯片设计

本文提出了一种具有高线性度的折叠,插值结构数模转换器(ADC)。与高速并行数模转换器(Flash ADC)相比较,该结构具有面积小,功耗低的特点,适用于低功耗超宽带(UWB)接收机中。本文对电路各部分进行了设计,并在SMIC 0.18μm工艺下完成了版图设计和后仿真。版图核心电路面积(不包括PAD)仅为0.45mm2,在1G samples/s采样率,输入信号为488.77MHz时,总功耗仅为57mW,有效位(ENOB)达到5.74bits。     

A 1-V low power gain boosted self-cascoding current mirror operational transconductance amplifier

A low-voltage, micro-power, low-noise, high-gain, high-output swing current mirror-based operational transconductance amplifier (OTA) is presented. The proposed OTA achieves high DC gain and output swing by the adoption of gain boosted current mirroring and self-cascoding techniques. From the simulation, the proposed OTA implemented on a 0.18 μm CMOS shows the DC gain up to 90 dB with a gain bandwidth of 700 KHz for a load capacitor of 1 pF and an output voltage swing of 600 mV. The OTA dissipates only 750 nW from 1.0 V supply.     

一种应用于流水线ADC的14-bit 50MS/s 采样保持电路

A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differential folded cascode operational transconductance amplifier. A double-bootstrapped switch is designed to improve the performance of the circuit. The circuit is implemented using a 0.18 μm 1P6M CMOS process. Measurement results show that the effective number of bits is 14.03 bits, the spurious free dynamic range is 94.62 dB, the signal to noise and distortion ratio is 86.28 dB, and the total harmonic distortion is -91.84 dB for a 5 MHz input signal with 50 MS/s sampling rate. A pipeline ADC with the designed S/H circuit has been implemented.     

一个具有改进开关逻辑的12位1MHz采样速率的低功耗逐次逼近型模数转换器

作为数据采集系统中的关键模块,逐次逼近型模数转换器的功耗决定了整个系统的功耗水平。本文给出了一个具有改进开关逻辑的12位1MHz采样速率的低功耗逐次逼近型模数转换器。通过采用所提出的开关逻辑,该逐次逼近型模数转换器的功耗和面积跟采用传统开关逻辑的逐次逼近型模数转换器相比都会有很大的降低,其中开关逻辑的平均功耗大约降低了80%,总的电容面积减小50%。不仅如此,文章还提出了一种简化的数字控制逻辑来降低数字控制电路的功耗和面积。仿真结果表明和传统的数字控制逻辑电路相比,提出的简化数字逻辑的功耗可以减小大约50%。所设计的芯片在标准的0.35微米的CMOS工艺下进行了流片,芯片内核的面积为1.12平方毫米。在-55℃到150℃温度变化范围下,芯片100KHz的输入信号可以测得64.2dB的SNDR。在给定3.3V的电源电压下,芯片的功耗仅为0.72mW。     

一种8位100 MS/s的低功耗流水线型ADC

基于0.35 μm CMOS工艺,设计并制作了一种低功耗流水线型ADC。分析了ADC结构对功耗的影响,采用1.5位/级的流水线结构来最小化功耗,并提升速度。为进一步降低功耗,设计了一种不带补偿并可调节相位裕度的共源共栅跨导放大器(OTA)和改进的比较器。测试结果显示,该ADC在3 V电源电压、100 MS/s采样速率下,功耗为65 mW,面积为0.73 mm²,在模拟输入频率为70.1 MHz和141 MHz下的无杂散动态范围(SFDR)分别为59.8 dBc和56.5 dBc。该ADC可应用于需要欠采样的通信系统中。     

A 10-bit low power SAR A/D converter based on 90 nm CMOS

Traditional and some recently reported low power, high speed and high resolution approaches for SAR A/D converters are discussed. Based on SMIC 65 nm CMOS technology, two typical low power methods reported in previous works are validated by circuit design and simulation. Design challenges and considerations for high speed SAR A/D converters are presented. Moreover, an R-C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process. The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively. With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively, and the power dissipation is measured to be just 3.17 mW.     

基于90nm CMOS工艺的一种10位低功耗SAR A/D转换器

Traditional and some recently reported low power,high speed and high resolution approaches for SAR A/D converters are discussed.Based on SMIC 65 nm CMOS technology,two typical low power methods reported in previous works are validated by circuit design and simulation.Design challenges and considerations for high speed SAR A/D converters are presented.Moreover,an R–C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process.The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively.With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively,and the power dissipation is measured to be just 3.17 mW.     

流水线ADC低功耗结构研究

介绍了一种50 MHz,10位,5V流水线模数转换器的设计.为实现低功耗设计目标,将比较器和OTA作为主要优化对象,采用改进的动态比较结构和套筒式余量放大器(OTA)分别实现上述功能.本设计在0.5μm CMOS工艺下实现,工作在50 MHz条件下功耗为190 mW.     

一个低功耗的带片上参考电压缓冲器的12位30兆采样率的CMOS流水线模数转换器

介绍了一个在0.13µm 1P8M CMOS工艺下实现的12位30兆采样率流水线模数转换器。提出了一种消除前端采样保持电路的低功耗设计方法。除了第一级之外,带双输入的两级cascode补偿的运算放大器在相邻级间共享以进一步地减小功耗。该模数转换器在5MHz的模拟输入和30.7MHz的采样速率下达到了65.3dB的SNR,75.8dB的SFDR和64.6dB的SNDR。该芯片在1.2V电源电压下消耗33.6mW。FOM达到了0.79pJ/conv step。