2GS/s 6-bit 自校准快闪ADC

A single channel 2-GS/s 6-bit ADC with cascade resistive averaging and self foreground calibration is demonstrated in 0.18-μ m CMOS. The calibration method based on DAC trimming improves the linearity and dynamic performance further. The peak DNL and INL are measured as 0.34 and 0.22 LSB, respectively. The SNDR and SFDR have achieved 36.5 and 45.9 dB, respectively, with 1.22 MHz input signal and 2 GS/s. The proposed ADC, including on-chip track-and-hold amplifiers and clock buffers, consumes 570 mW from a single 1.8 V supply while operating at 2 GS/s.     

单通道8bit1.4GS/s折叠内插ADC

基于0.18 μm CMOS工艺设计并实现了一种8 bit 1.4 GS/s ADC.芯片采用多级级联折叠内插结构降低集成度,片内实现了电阻失调平均和数字辅助失调校准.测试结果表明,ADC在1.4GHz采样率下,有效位达6.4bit,功耗小于480 mW.文章所提的综合校准方法能够有效提高ADC的静态和动态性能,显示出...     

一种10位100-MS/s CMOS流水折叠式A/D转换器

采用流水折叠结构设计了一种10位100-MSample/s A/D转换器。失调取消技术和电阻平均插值网络提高了转换器的线性度。级联结构放宽了折叠放大器的带宽要求,采用分布式级间跟踪保持放大器实现流水线技术来获得更高的转换精度。基于SMIC 0.18 μm CMOS工艺的测试结果如下：INL和DNL的峰值分别为0.48 LSB and 0.33 LSB。输入电压范围VP-P为1.0 V,芯片面积2.29 mm2。100 MHz采样,20 MHz输入信号下,ENOB为9.59位,SNDR为59.5 dB,SFDR为82.49 dB。1.8V电源电压下功耗仅为95 mW。     

一种速度优化的流水线模数转换电容误差平均技术

无源电容误差平均技术是一种本质线性(Inherently Linear)的流水线模数转换电容失配校准技术,但其转换速度是传统技术的一半.为了提高速度,本文提出了一种改进的电容误差平均技术.该技术从减少一个转换周期所需的时钟相数目和减少每个时钟相的时间两个方面来优化速度.电路分析和MATLAB仿真表明,在两种典型的情况下,改进的技术能将速度提高52%(跨导放大器为开关电容共模反馈)和64%(跨导放大器为非开关电容共模反馈)以上.改进的技术更适用于高速高精度及连续工作的应用场合.     

Differential Hot Electron Injection in an Adaptive Floating Gate Comparator

We introduce differential-mode hot electron injection for adapting and storing analog nonvolatile signed state variables. This approach is compatible with modern digital CMOS technologies and is readily extended to novel circuit applications. We highlight advantages of the technique by applying it to the design of an adaptive floating gate comparator (AFGC). This is the first use of this technique for adaptation in a nonlinear circuit. The AFGC computes appropriate voltages for locally adapting the input floating gate nodes to cancel offsets. The technique is amenable to both local and nonlocal adaptation which allows greater design flexibility.The AFGC has been fabricated in a commercially available 0.35 μm CMOS process. We experimentally demonstrate more than two orders of magnitude reduction in offset voltage: the mean offset is reduced by 416X relative to chips direct from the foundry and by 202X relative to UV-irradiated chips. We consider both static and dynamic adaptation and demonstrate that the the accuracy of dynamic offset cancellation is approximately two orders of magnitude better than static adaptation. In the presence of observed 8% injection mismatch, the AFGC robustly converges to within 728 μV of the desired input offset (mean offset −109 μV, standard deviation 379 μV). Adaptation occurs within milliseconds, with charge retention for more than one month, and variation of offset error with temperature of −15 μV/^∘C.Yanyi Liu Wong received the B.S. and M.S. degrees in Electrical Engineering in 2001 and 2004, respectively, from the University of Maryland, College Park, where he is currently working toward the Ph.D. degree. From 2001 to 2003, he was a Teaching Assistant for microelectronics lectures and labs. Since 2003, he has been with The Johns Hopkins University Applied Physics Laboratory developing Radiation-Hardened-By-Design EEPROM subsystems for space based ASICs. At the same time, he has been working as a Research Assistant at the Integrated Biomorphic Information Systems Laboratory, UMCP, and has been actively designing low-power, mixed-signal, adaptive floating gate circuits and applications in commercially available CMOS processes.Marc H. Cohen received both B.Sc. and M.Sc. degrees in Electrical Engineering from the University of the Witwatersrand, Johannesburg, South Africa in 1978 and 1983 respectively. He received an M.S. in Biomedical Engineering and a Ph.D. in Electrical and Computer Engineering from The Johns Hopkins University, Baltimore, MD, USA in 1991 and 2001 respectively. He is currently an Assistant Research Scientist in the Institute for Systems Research, University of Maryland, College Park. His research interests lie in the areas of adaptive low power analog and mixed-signal integrated circuit design. Current application areas include ultrasonic echolocation, contact imagers for control of microfluidic devices, controllers for adaptive optics and integrated sensors for RFID.Pamela A. Abshire received the B.S. degree in physics with honor in 1992 from the California Institute of Technology. Between 1992 and 1995 she worked as a Research Engineer in the Bradycardia Research Department of Medtronic, Inc. She received her M.S. and Ph.D. degrees in Electrical and Computer Engineering from The Johns Hopkins University in 1997 and 2002, respectively. She is currently an assistant professor in the Department of Electrical and Computer Engineering and the Institute for Systems Research at the University of Maryland, College Park. Dr. Abshire’s research focuses on low power mixed signal integrated circuit design, adaptive integrated circuits, integrated circuits for biosensing, and understanding the tradeoffs between performance and energy in natural and engineered systems.     

一种CMOS折叠结构ADC中的失调抵消技术

CMOS折叠预放电路的失调是限制CMOS折叠结构A/ D转换器实现高分辨率应用的主要原因之一.文中提出差分对的动态匹配技术改善了折叠预放电路的失调,从而为研制CMOS工艺中的高分辨率折叠结构A/ D转换器提供了一种可行方案,并给出了MATL AB和电路仿真的实验结果.     

一种CMOS动态闩锁电压比较器的优化设计

提出了一种应用于Pipeline ADC和Sigma-Delta ADC中改进的动态闩锁电压比较器。采用0.35μm CMOS N阱工艺设计,工作于2.5V单电源电压。通过详细的分析和优化,使比较器具有较小的输入失调电压和踢回噪声,仿真结果表明它的输入失调电压分布范围为28.6mV,最高工作频率200MHz、功耗230μW。     

一个10位、50MS/s CMOS折叠流水结构A/D转换器

在 0.6μmDPDM标准数字CMOS工艺条件下 ,实现 10位折叠流水结构A/D转换器 ,使用动态匹配技术 ,消除折叠预放电路的失调效应 ;提出基于单向隔离模拟开关的分步预处理 ,有效压缩了电路规模 ,降低了系统功耗 .在5V电源电压下 ,仿真结果为 :当采样频率为50MSPS时 ,功耗为 12 0mW ,输入模拟信号和二进制输出码之间延迟为2.5个时钟周期 ,芯片面积 1.44mm2 .     

一种用于流水线模数转换器的电容失配校准方法

对于流水线模数转换器(ADC),电容失配是一种主要的非线性误差源. 为了减小电容失配误差,提出了一种电容失配校准的方法. 该方法通过一种电荷相加、电容交换和电荷反转移的电路技术,可将电容失配误差减小至其2次项. 基于所提出的方法,设计了一种0.6μm CMOS,13b, 2MS/s的流水线ADC实验芯片. 对所设计的实验芯片进行测试,得到了0.5LSB的DNL和2.5LSB的INL,并且当以614kHz的采样率对19.2kHz的输入进行转换时,得到了71.2dB的SFDR和64.1dB的SNDR,当以2MHz的采样率对125kHz的输入进行转换时,得到了70.6dB的SFDR和62.22dB的SNDR. 以上结果表明,ADC得到了超出电容匹配精度的线性度,证明了所采用的电容失配校准方法的有效性.     

一种新型红外焦平面片上模数转换电路

基于串行单斜率积分的原理,提出了一种新型的像素级红外焦平面片上8位模数转换电路.设计了一个8×8像素阵列组成的完整读出电路芯片,并进行了版图设计和电路仿真.每个单元像素电路采用直接注入方式输入,输出与输入电流成正比的数字脉冲信号,经每列单元共享的计数器计数输出.采用独特的数字电路列共享结构,电荷注入补偿等技术,具有结构简单、面积小等特点.仿真及测试结果表明,该芯片能较好地完成红外焦平面信号读出及模数转换功能,单元面积80 μm×80 μm,单元功耗50 μW,量化等级达到8位,芯片实测量化误差小于4 LSB,帧速可达460 f/s.     

0.35μm CMOS 4位1 Gsample/s全并行模数转换器设计

介绍了一种基于0.35μm CMOS工艺的4位最大采样速率为1GHz的全并行结构模数转换器的设计.因为在高采样率的情况下,比较器的亚稳态问题降低了模数转换器的无杂散动态范围,在本次设计中对其进行了优化.后仿真结果表明,输入信号为22.949MHz,在1GHz采样率的情况下,信噪比达到25.08dB,积分非线性和微分非线性分别小于0.025LSB和0.01LSB,无杂散动态范围达到32.91dB.芯片采用具有两层多晶硅的0.35μmCMOS工艺设计,总面积为0.84mm2.     

逐次逼近（SAR）模数转换器进展

介绍了逐次逼近模数转换器（SAR－ADC）的原理结构和研究现状,主要对SAR－ADC 中的DAC、比较器、校准方法等主要模块进行了讨论。基于精度、速度、功耗的考虑,分别对SAR－ADC中的DAC结构进行分析比较,其多采用分段电容阵列或差分电容阵列。简述了比较器在功耗、速度、精度方面的结构调整。基于降低非理想效应,提高精度目的,对比分析了3种校准方法。为不同电路选择适当校准提供参考依据。最后总结了目前SAR－ADC的发展趋势。     

一种应用于低压CMOS差分放大器的失调取消技术

基于对CMOS差分放大器的非线性和元件失配理解的基础上,提出了一种应用于低电压CMOS差分放大器的失调取消技术.这种技术在不需要增加功耗的基础上,通过把输出端的失调电压转移到差分放大器的其他节点,从而达到减小输入参考的失调电压的目的.为了验证这种技术,设计了一个工作电压为1.8V的低失调的CMOS差分放大器.仿真结果表明,在负载晶体管的失配为20%,输入放大管的失配为10%时,利用这种失调转移技术,输入参考的失调可以减少40%.同已发表的失调取消技术相比,利用这种技术可以达到更低的功耗和更高的集成度.     

A Novel Offset-Cancellation Technique for Low Voltage CMOS Differential Amplifiers

基于对CMOS差分放大器的非线性和元件失配理解的基础上,提出了一种应用于低电压CMOS差分放大器的失调取消技术.这种技术在不需要增加功耗的基础上,通过把输出端的失调电压转移到差分放大器的其他节点,从而达到减小输入参考的失调电压的目的.为了验证这种技术,设计了一个工作电压为1.8V的低失调的CMOS差分放大器.仿真结果表明,在负载晶体管的失配为20%,输入放大管的失配为10%时,利用这种失调转移技术,输入参考的失调可以减少40%.同已发表的失调取消技术相比,利用这种技术可以达到更低的功耗和更高的集成度.     

一种采用数字前端校正技术的8位超高速时间交叠折叠/内插模-数转换器

本文呈现了一种0.35微米BiCMOS工艺下采样率为2GSPS的8位模数转换器。此ADC采用独特的折叠/内插算法,利用双通道间的时钟交叠复合技术,可以获得2GSPS的采样率。对S/H电路的失调误差与增益误差、前置放大器的失调误差、通道间的增益误差与时钟相位误差进行校正。测试结果表明,芯片在自校正工作状态下,模拟输入为484MHz时,ENOB为7.32位,而在Nyquist输入频率下ENOB为7.1位。     

一种滞回比较器设计

比较器广泛应用于模拟信号到数字信号的转换过程中,在模-数转换过程中,对输入进行采样后的信号通过比较器以决定模拟信号的数字量。滞回比较器也叫迟滞比较器,以其优越的抗噪声能力在比较器中占有重要地位。描述一种滞回比较器,使用少量元件节省成本,滞回电压阈值设计灵活,同时用P管作差分输入管,有较高的共模输入范围,转换速率快。使用0.18μm CMOS工艺分别对转折点压差为200 m V的设计进行仿真,仿真结果与设计预期相符合。     

应用于CMOS图像传感器中带有失调电压消除功能的电容比值非相关十位循环式模数转换器

A 10-bit ratio-independent switch-capacitor（SC） cyclic analog-to-digital converter（ADC） with offset cancelingforaCMOSimagesensorispresented.TheproposedADCcompletesanN-bitconversionin1.5N clock cycles with one operational amplifier. Combining ratio-independent and polarity swapping techniques, the conversioncharacteristicoftheproposedcyclicADCisinherentlyinsensitivebothtocapacitorratioandtoamplifieroffset voltage. Therefore, the circuit can be realized in a small die area and it is suitable to serve as the column-parallel ADC in CMOS image sensors. A prototype ADC is fabricated in 0.18- m one-poly four-metal CMOS technology.The measured results indicate that the ADC has a signal-to-noise and distortion ratio（SNDR） of 53.6 dB and a DNL of C0：12/0：14 LSB at a conversion rate of 600 kS/s. The standard deviation of the offset variation of the ADC is reduced from 2.5 LSB to 0.5 LSB. Its power dissipation is 250 W with a 1.8 V supply, and its area is0.030.8 mm2.     

80dB动态范围，用于低中频结构GSM接收机的ΣΔ调制器

介绍了一个200kHz信号带宽、用于低中频结构GSM射频接收机的高精度ΣΔ调制器.该调制器采用3阶单环单比特的结构,电路使用全差分开关电容结构实现,并在0.6μm 2P2M CMOS工艺下流片验证.调制器使用全差分±1V参考电压,工作在26MHz采样频率,过采样率为64.测试结果表明,在200kHz信号带宽内,调制器达到80.6dB动态范围,峰值SNDR达到71.8dB,峰值SNR达到73.9dB.整个调制器电源电压为5V,静态功耗为15mW.