2GS/s 6-bit 自校准快闪ADC

A single channel 2-GS/s 6-bit ADC with cascade resistive averaging and self foreground calibration is demonstrated in 0.18-μ m CMOS. The calibration method based on DAC trimming improves the linearity and dynamic performance further. The peak DNL and INL are measured as 0.34 and 0.22 LSB, respectively. The SNDR and SFDR have achieved 36.5 and 45.9 dB, respectively, with 1.22 MHz input signal and 2 GS/s. The proposed ADC, including on-chip track-and-hold amplifiers and clock buffers, consumes 570 mW from a single 1.8 V supply while operating at 2 GS/s.     

单通道8bit1.4GS/s折叠内插ADC

基于0.18 μm CMOS工艺设计并实现了一种8 bit 1.4 GS/s ADC.芯片采用多级级联折叠内插结构降低集成度,片内实现了电阻失调平均和数字辅助失调校准.测试结果表明,ADC在1.4GHz采样率下,有效位达6.4bit,功耗小于480 mW.文章所提的综合校准方法能够有效提高ADC的静态和动态性能,显示出...     

一种10位100-MS/s CMOS流水折叠式A/D转换器

采用流水折叠结构设计了一种10位100-MSample/s A/D转换器。失调取消技术和电阻平均插值网络提高了转换器的线性度。级联结构放宽了折叠放大器的带宽要求,采用分布式级间跟踪保持放大器实现流水线技术来获得更高的转换精度。基于SMIC 0.18 μm CMOS工艺的测试结果如下：INL和DNL的峰值分别为0.48 LSB and 0.33 LSB。输入电压范围VP-P为1.0 V,芯片面积2.29 mm2。100 MHz采样,20 MHz输入信号下,ENOB为9.59位,SNDR为59.5 dB,SFDR为82.49 dB。1.8V电源电压下功耗仅为95 mW。     

A 10-bit 100-MS/s CMOS pipelined folding A/D converter

This paper presents a 10-bit 100-MSample/s analog-to-digital（A/D） converter with pipelined folding architecture.The linearity is improved by using an offset cancellation technique and a resistive averaging interpolation network.Cascading alleviates the wide bandwidth requirement of the folding amplifier and distributed interstage track/hold amplifiers are used to realize the pipeline technique for obtaining high resolution.In SMIC 0.18μm CMOS,the A/D converter is measured as follows:the peak integral nonlinearity and differential nonlinearity are±0.48 LSB and±0.33 LSB,respectively.Input range is 1.0 V_P-P with a 2.29 mm² active area.At 20 MHz input @ 100 MHz sample clock,9.59 effective number of bits,59.5 dB of the signal-to-noise-and-distortion ratio and 82.49 dB of the spurious-free dynamic range are achieved.The dissipation power is only 95 mW with a 1.8 V power supply.     

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier for an IR-UWB receiver

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier(THA) in 0.13μm CMOS for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency.This paper presents,to our knowledge for the second time,a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz.In this design,a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz.A resistive averaging technique is carefully analyzed to relieve noise aliasing.A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed,power consumption and noise aliasing.The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s.The core power of the ADC is 30 mW,excluding all of the buffers,and the active area is 0.6 mm~2.The ADC achieves a figure of merit of 3.75 pJ/conversion-step.     

一个5-bit 4 GS/s的插值型模数转换器设计

设计了一款5-bit 4 GS/s的电阻插值型模数转换器(ADC),由预放大器阵列、高速比较器和编码器模块组成。定量分析了预放大器阵列的带宽和增益对ADC性能的影响,选取了最优的预放大器阵列结构,采样保持电路则选择了分布式采样,并采用电流逻辑模(CML)的比较器和编码电路。基于TSMC 65 nm工艺下进行仿真:在4 GHz的采样频率下,输入信号为200 MHz时,有效位数(ENOB)为4.85,SNDR为30.97,系统功耗为85 m W。     

一款具有新颖的采样保持电路应用于脉冲式超宽带技术的欠采样型模数转换器

本文提出了一款基于CMOS 0.13um,具有新颖的采样保持电路,应用于脉冲式超宽带接收机的欠采样型模数转换器.本文主要的难点在于实现拥有远远高于奈奎斯特频率的输入信号的欠采样型模数转换器。根据我们的了解,本文是当今第二次提出当采样时钟大约在1.056GHz,输入信号超过4GHz的欠采样型模数转换器。电路设计中,我们提出了一款新颖的采样保持电路,解决了信号幅度的衰减和高频输入信号线性度的问题。一款使用零静态功耗动态失调校准比较器被进一步优化,实现了失调,速度以及功耗的要求。测试结果显示,当采样频率为1.056GHz,输入信号高达4.2GHz时,SFDR 为30.1dB。不包括缓冲器,ADC的功耗为30mW,芯片面积为0.6mm2.ADC的FoM是3.75pJ.     

A 12-bit 100 MS/s pipelined ADC with digital background calibration

This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC) with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter (MDAC) while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3×1.6 mm~2, and consumes 205 mW at 1.8 V.     

一个带有采样时间误差校正的14位200MS/s时钟交织模数转换器

通道间的采样时间误差会降低时钟交织模数转换器的精度。本论文提出了一种针对采样时间误差的具有低电路复杂度和快速收敛特性的校正算法。该算法基于相关性来探测采样时间误差,并可被应用于广义平稳的输入信号,被探测到的采样时间误差被一个压控采样开关修正。实验结果显示,对于一个2通道14位200MS/s的时钟交织模数转换器,当输入信号的频率为70.12MHz时,经校正后,信号与噪声失真比改善了19.1dB,无杂散动态范围改善了34.6dB。校正的收敛时间约为20000个采样时间间隔。     

采用后台数字校准的12位100MHz流水线模数转换器

This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter （MDAC） while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3 × 1.6 mm^2, and consumes 205 mW at 1.8 V.     

A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS

This paper presents a 25-GS/s 6-bit time-interleaved (TI) SAR ADC in a 40-nm CMOS low-leakage (LL) process. The prototype utilizes 4 × 12 hierarchical sampling architecture to reduce the complexity of track-and-hold circuits and the timing skew calibration. The single-channel SAR ADC adopts asynchronous processing with two alternate comparators. A partially active reference voltage buffer is designed to reduce the power consumption. The method based on sinusoidal signal approximation is employed to calibrate timing skew errors. To characterize the ultra-high-speed ADC, an on-chip design-for-test memory is designed. At 25 GS/s, the ADC achieves the SNDR of 32.18 dB for low input frequency and 27.28 dB for Nyquist frequency. The chip consumes 800 mW and occupies 1.3 × 2.6 mm², including the TI ADC core and memory.     

5-bit 1.25GS/s Flash ADC的设计及数字后台校正的实现

-本文设计了一款高速的全并行模数转换器,并基于Volterra级数设计了校正反模型,对此款ADC进行了数字后台校正。首先,基于0.18 CMOS设计了一个采样频率为1.25GHz分辨率为5位的Flash ADC,该ADC采用分布式采保结构对输入信号进行量化。同时,基于Volterra级数,实现了数字后台校正模型的设计,并基于此模型对所设计的高速Flash ADC的非线性进行了补偿和校正。仿真结果表明,ADC的输出信号谐波得到了很好的抑制,当输入信号频率为117.1M时,有效位数达到了4.83bit;当输入信号接近奈奎斯特频率时,有效位数达到了4.74bit。     

一种低功耗11位100MS/s采样率SAR ADC IP

本文介绍了一种双通道11位100MS/s采样率的混合结构SAR ADC IP。每个通道均采用flash-SAR结构以达到高速低功耗的目的。为了进一步降低功耗,flash和SAR中的比较器均采用全动态比较器。SAR中逐次逼近逻辑所需要的高速异步触发时钟采用门控环形振荡器产生。为了提高电容的匹配性,在版图设计中,采用底板包围顶板的MOM电容结构,有效减小电容寄生。本设计制造工艺为SMIC55nm的低漏电CMOS工艺,双通道的总面积为0.35mm2且核心面积仅为0.046 mm2。双通道模数转换器在1.2V供电电压下消耗的总电流为2.92mA。在2.4MHz输入和50MHz输入下的有效转换位数（ENOB）分别为9.9位和9.34位。计算得出本设计的FOM值为18.3fJ/conversion-step。     

一种用于14位250 MS/s ADC的3.5 Gb/s发送器

提出了一种用于14位250 MS/s ADC的数据发送器。该发送器输出采用电流模驱动方式,最高数据传输速率达3.5 Gb/s,数据输出仅需要2个数据端口。电路采用180 nm 1.8 V 1P5M CMOS工艺实现。测试结果表明,该发送器在3.5 Gb/s速率下的输出信号摆幅为800 mV,抖动峰峰值为100 ps,功耗为32 mW。采用该3.5 Gb/s数据发送器的ADC在250 MHz采样率下得到的信噪比为71.1 dBFS,无杂散动态范围为77.6 dB。     

A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS

A 6-bit 3.5-GS/s flash ADC is reported. A load circuit with a clamp diode and a replica-biasing scheme is developed for low-voltage and high-speed operation. An acceleration capacitor is introduced for high-speed overdrive recovery of a comparator. An averaging and interpolation network is employed in this ADC. The interpolation factor is optimized considering random offset, active area, and systematic offset to realize low offset and small active area. The ADC is fabricated in a 90-nm CMOS process and occupies 0.15 mm². It consumes 98 mW with a 0.9-V power supply. With Nyquist input, SNDR and SFDR at 3.5 GS/s are 31.18 dB and 38.67 dB, respectively.     

一个10位、50MS/s CMOS折叠流水结构A/D转换器

在 0.6μmDPDM标准数字CMOS工艺条件下 ,实现 10位折叠流水结构A/D转换器 ,使用动态匹配技术 ,消除折叠预放电路的失调效应 ;提出基于单向隔离模拟开关的分步预处理 ,有效压缩了电路规模 ,降低了系统功耗 .在5V电源电压下 ,仿真结果为 :当采样频率为50MSPS时 ,功耗为 12 0mW ,输入模拟信号和二进制输出码之间延迟为2.5个时钟周期 ,芯片面积 1.44mm2 .     

一种基于二进制搜索每级输出2位的6-bit 230-MS/s单通道异步逐次逼近模数转换器

This paper proposes a single channel, 6-bit 230-MS/s asynchronous successive approximation register analog-to-digital converter （ADC） in an SMIC 65 nm CMOS technology. Through adopting the modified 2 bits/stage asynchronous control logic, the presented ADC actualizes a peak 40.90-dB spurious-free dynamic range and 29.05-dB signal-to-noise and distortion ratio at 230-MS/s sampling rate. Utilizing the dynamic comparator without the preamplifier, this work attains low-power design with only 0.93 mW power consumption and accomplishes a figure of merit of 174.67 fJ/step at 1 V supply voltage.     

A 12-bit 40 MS/s pipelined ADC with over 80 dB SFDR

This paper describes a 12-bit 40 MS/s calibration-free pipelined analog-to-digital converter (ADC), which is optimized for high spurious flee dynamic range (SFDR) performance and low power dissipation. With a 4.9 MHz sine wave input, the prototype ADC implemented in a 0.18-μm 1P6M CMOS process shows measured differential nonlinearity and integral nonlinearity within 0.78 and 1.32 least significant bits at the 12-bit level without any trimming or calibration. The ADC, with a total die area of 3. 1 × 2.1 mm~2, demonstrates a maximum signal-to-noise distortion ratio (SNDR) and SFDR of 66.32 and 83.38 dB, respectively, at a 4.9 MHz analog input and a power consumption of 102 mW from a 1.8 V supply.     

一个SFDR性能超过80dB的12-bit 40MS/s流水线模数转换器

摘要：本文介绍了一个以高无杂散动态范围(SFDR)和低功耗为优化目标,不需要校正的12-bit,40MS/s流水线模数转换器(ADC)。以4.9MHz正弦输入信号测试表明,本ADC微分非线性(DNL)的最大值为0.78LSB,积分非线性(INL)的最大值为1.32LSB,信噪失真比(SNDR)为66.32dB,SFDR为83.38dB。电路采用 0.18-um 1P6M CMOS工艺实现,整体芯片面积3.1mm×2.1mm,电源电压1.8V,功耗102mW。     

A 10-bit 50-MS/s subsampling pipelined ADC based on SMDAC and opamp sharing

This paper describes a 10-bit,50-MS/s pipelined A/D converter(ADC) with proposed area- and power-efficient architecture.The conventional dedicated sample-hold-amplifier(SHA) is eliminated and the matching requirement between the first multiplying digital-to-analog converter(MDAC) and sub-ADC is also avoided by using the SHA merged with the first MDAC(SMDAC) architecture,which features low power and stabilization.Further reduction of power and area is achieved by sharing an opamp between two successive pi...