基于斜坡电荷泵控制的高速低抖动锁相环

本文提出了一种新型高速低抖动锁相环架构。通过实时监测鉴频鉴相器的输出产生线性斜坡电荷泵电流,实现了自适应带宽控制。主要通过在传统锁相环的基础上,巧妙地设计了一个快速启动电路和一个斜坡电荷泵电路。首先,使能快速启动电路实现对环路滤波器的快速预充电;然后当鉴频鉴相器输出的充电电流脉宽超过设定的最小值时,斜坡电流控制电路将线性增加电荷泵电流,从而实现了快速响应和低相位噪声。同时,通过零温度系数电荷泵电流的设计,保证了高速低抖动指标的温度稳定性。所设计的新型锁相环架构已在一款基于0.35 μm的DSP处理芯片中得到验证。测试结果显示所设计斜坡电荷泵锁相环在宽温度范围内使得锁定时间提高了60%,且峰峰值抖动仅有0.3%的良好特性。     

锁相环频率综合器中高性能电荷泵设计

本文基于0.18μm CMOS工艺设计并实现了一种新的高性能电荷泵电路。采用宽输入范围的轨到轨运算放大器和自偏置共源共栅电流镜技术提高了电荷泵在宽输出电压范围内的电流匹配精度;同时,提出通过增加预充电电流源技术来提高电荷泵的初始充电电流,以缩短CPPLLs的建立时间。测试结果表明电荷泵在0.4～1.7V输出电压范围内失配电流小于0.4%,充电电流为100μA,预充电电流为70μA。在1.8V电源电压下,电荷泵电路锁定时的平均功耗为0.9mW。     

Phase-locked loop design with fast-digital-calibration charge pump

A fast-digital-calibration technique is proposed for reducing current mismatch in the charge pump (CP) of a phase-locked loop (PLL). The current mismatch in the CP generates fluctuations, which is transferred to the input of voltage-controlled oscillator (VCO). Therefore, the current mismatch increases the reference spur in the PLL. Improving current match of CP will reduce the reference spur and decrease the static phase offset of PLLs. Moreover, the settling time, ripple and power consumption of the PLL are also improved by the proposed technique. This study evaluated a 2.27–2.88 GHz frequency synthesiser fabricated in TSMC 0.18 μm CMOS 1.8 V process. The tuning range of proposed VCO is about 26%. By using the fast-digital-calibration technique, current mismatch is reduced to lower than 0.97%, and the operation range of the proposed CP is between 0.2 and 1.6 V. The proposed PLL has a total power consumption of 22.57 mW and a settling time of 10 μs or less.     

Design of a high performance CMOS charge pump for phase-locked loop synthesizers

A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range.Furthermore,a method of adding a precharging current source is proposed to increase the initial charge current,which will speed up the settling time of CPPLLs.Test results show that the current mismatching can be less than 0.4%in the output voltage range of 0.4 to 1.7 V,with a charge pump current of 100μA and a precharging current of 70μA.The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.     

一种低抖动电荷泵锁相环的设计

采用动态鉴频鉴相器、基于常数跨导轨到轨运算放大器的电荷泵、差分型环形压控振荡器,设计了一种低抖动的电荷泵锁相环。基于SMIC 0.18-μm CMOS工艺,利用Cadence软件完成了电路的设计与仿真。结果表明,动态的鉴频鉴相器,有效消除了死区。新型的电荷泵结构,在输出电压为0.5 V~1.5 V时将电流失配减小到了2%以下。压控振荡器在频率为1 MHz时输出的相位噪声为-94.87 dB在1 MHz,调谐范围为0.8 GHz~1.8 GHz。锁相环锁定后输出电压波动为2.45 mV,输出时钟的峰峰值抖动为12.5 ps。     

Design and noise analysis of a fully-differential charge pump for phase-locked loops

A fully-differential charge pump (FDCP) with perfect current matching and low output current noise is realized for phase-locked loops (PLLs). An easily stable common-mode feedback (CMFB) circuit which can handle high input voltage swing is proposed. Current mismatch and current noise contribution from the CMFB circuit is minimized. In order to optimize PLL phase noise, the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle. The calculation result agrees well with the simulation. Based on the noise analysis, many methods to lower output current noise of the FDCP are discussed. The fully-differential charge pump is integrated into a 1-2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18 μm process. The measured output reference spur is -64 dBc to -69 dBc. The in-band and out-band phase noise is -95 dBc/Hz at 3 kHz frequency offset and -123 dBc/Hz at 1 MHz frequency offset respectively.     

一种应用于频率综合器的全差分电荷泵的设计与噪声分析

A fully-differential charge pump（FDCP）with perfect current matching and low output current noise is realized for phase-locked loops（PLLs）.An easily stable common-mode feedback（CMFB）circuit which can handle high input voltage swing is proposed.Current mismatch and current noise contribution from the CMFB circuit is minimized.In order to optimize PLL phase noise,the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle.The calculation result agrees well with the simulation.Based on the noise analysis,many methods to lower output current noise of the FDCP are discussed.The fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18μm process.The measured output reference spur is–64 dBc to–69 dBc.The in-band and out-band phase noise is–95 dBc/Hz at 3 kHz frequency offset and–123 dBc/Hz at 1 MHz frequency offset respectively.     

基于电荷泵锁相环的有源环路滤波器的设计

环路滤波器是锁相环中的一个关键模块,对宽带高压VCO进行调谐时,常采用有源滤波器。在论述了电荷泵锁相环基本原理的基础上,对有源环路滤波器的结构以及滤波器对锁相环性能的影响进行了分析,推导出有源环路滤波器参数的设计方法。根据课题设计了三阶有源环路滤波器,用ADS工具对锁相环系统性能进行仿真,仿真结果与理论相吻合。实验结果表明,所设计的滤波器满足了课题的要求,验证了本方法的正确性。     

A new all-digital phase-locked loop with high precision and low jitter

A new method is proposed in this article to accomplish the fine tune unit of the digitally controlled oscillator of an all-digital phase-locked loop (ADPLL). Instead of using adjustable currents, we utilise the difference of the equivalent capacitance obtained from the drain of MOS transistors between on and off states as the fine tune delay parameter. Based on post-layout simulation results, the time resolution of the fine tune delay element can achieve results as good as 1.7126 ps. The operating frequency of this presented ADPLL ranges from 308 to 587 MHz. As compared to prior arts, the power consumption per MHz is reduced over 15% and the jitter is as low as 5 ps, which is a significant improvement.     

基于MATLAB的锁相环频率合成器教学实践

通信系统性能好坏很大程度上取决于有没有一个良好的同步系统。在“通信原理”课程中提到了基于锁相环的同步系统,但是对这部分内容介绍简单,没有系统的推导以及结论。基于Matlab的锁相环系统,能够得到不同参数下的锁相环的环路滤波器幅频响应和闭环响应,在Simulink工具箱中,设计一个基于锁相环的频率合成器,让学生掌握锁相环相位锁定的原理以及同步系统,为通信原理课程学习提供了支持。     

A low jitter supply regulated charge pump PLL with self-calibration

This paper describes a ring oscillator based low jitter charge pump PLL with supply regulation and digital calibration. In order to combat power supply noise, a low drop output voltage regulator is implemented. The VCO gain is tunable by using the 4 bit control self-calibration technique. So that the optimal VCO gain is automatically selected and the process/temperature variation is compensated. Fabricated in the 0.13 μ m CMOS process, the PLL achieves a frequency range of 100-400 MHz and occupies a 190×200 μ m² area. The measured RMS jitter is 5.36 ps at a 400 MHz operating frequency.     

A multiple-pass ring oscillator based dual-loop phase-locked loop

A dual-loop phase-locked loop (PLL) for wideband operation is proposed. The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one, enabling a wide tuning range and low voltage-controlled oscillator (VCO) gain without poisoning phase noise and reference spur suppression performance. An analysis of the phase noise and reference spur of the dual-loop PLL is emphasized. A novel multiple-pass ring VCO is designed for the dual-loop application. It utilizes both voltage-control and current-control simultaneously in the delay cell. The PLL is fabricated in Jazz 0.18-μm RF CMOS technology. The measured tuning range is from 4.2 to 5.9 GHz. It achieves a low phase noise of-99 dBc/Hz @ 1 MHz offset from a 5.5 GHz carrier.     

电荷泵PLL中PFD的设计

在电荷泵锁相环CP-PLL原理分析基础上,对其重要的组成模块鉴频鉴相器(PFD)进行了详细的理论分析和电路设计.在VCO的动态范围内,可实现任意频率误差下的快速频率跟踪,并最终实现零相位锁定.和一般的鉴相器比较,PFD工作在大的范围(-2π～ 2π),实现零相位误差.电路通过了基于上华0.5μmCMOS工艺的HSPICE模拟仿真验证,得到在5V电源电压和27MHz/s的参考频率下,PFD的增益Kpd为5/4πV/rad.     

一种基于环形振荡器的双环路锁相环

A dual-loop phase-locked loop（PLL）for wideband operation is proposed.The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one,enabling a wide tuning range and low voltage-controlled oscillator（VCO）gain without poisoning phase noise and reference spur suppression performance.An analysis of the phase noise and reference spur of the dual-loop PLL is emphasized.A novel multiple-pass ring VCO is designed for the dual-loop application.It utilizes both voltage-control and current-control simultaneously in the delay cell. The PLL is fabricated in Jazz 0.18-μm RF CMOS technology.The measured tuning range is from 4.2 to 5.9 GHz.It achieves a low phase noise of–99 dBc/Hz@1 MHz offset from a 5.5 GHz carrier.     

电荷泵锁相环环路滤波器参数设计与分析

从环路滤波器的基本概念出发,主要论述了电荷泵锁相环环路滤波器参数的设计方法(包括1阶,2阶,3阶环路滤波器),通过比较闭环的参数设计方法的不足,提出了一种新的开环环路滤波器参数的设计方法,并做出总结,最后利用Cadence公司Virtuoso系列主要对二阶无源低通滤波器进行仿真,验证了本方法的正确性,有一定的实用价值。     

应用锁相环技术判别混沌相变的方法

针对经典的李氏指数法(Lyapunov Exponential Method)等混沌相变判别方法复杂度高的问题,提出了一种应用锁相环技术判别混沌相变的新方法.首先,理论推导了混沌系统的解析特性,分析了系统在不同相态下含有的频率成分;然后,构建了针对混沌系统的数字锁相环模型,研究锁相环下混沌态和大周期态呈现的频率特性;最后,提出了一种基于锁相环技术的混沌相变判别新方法.仿真实验显示,相比于李氏指数法,所提方法判别速度快一个数量级,检测差错率为0时,性能提高近2 dB.新方法应用锁相环技术,简便易行,判别速度快,为混沌相变判别的工程应用提供了新的手段.     

一种500MHz高性能锁相环的设计

随着专用集成芯片（ASIC）和系统芯片（SOC）的飞速发展,芯片内部生成可变频率的稳定时钟变得至关重要,设计一个高性能锁相环正是适应了这样的需求。本文在传统锁相环结构的基础上设计了一种高速、低功耗、低噪声的高性能嵌入式混合信号锁相环结构。它可以在片内产生多分组高频稳定时钟信号,从而为先进的专用集成芯片（ASIC）和系统芯片（SOC）的实现提供最基础且最重要的可应用时钟产生电路。模拟结果表明：该锁相环可稳定输出500 MHz时钟信号,稳定时间小于700ns,在1．8V电源下的功耗小于18mW,噪声小于180mV。     

一种500MHz高性能锁相环的设计

在传统锁相环结构的基础上设计了一种高速、低功耗、低噪声的高性能嵌入式混合信号锁相环结构.它可以在片内产生多分组高频稳定时钟信号,从而为先进的专用集成芯片(ASIC)和系统芯片(SOC)的实现提供最基础且最重要的可应用时钟产生电路.模拟结果表明,该锁相环可稳定输出500MHz时钟信号,稳定时间小于700 ns,在1.8V电源下的功耗小于18mW,噪声小于180mV.     

Modeling and analysis of single-event transients in charge pumps

It has been shown that charge pumps (CPs) dominate single-event transient (SET) responses of phaselocked loops (PLLs). Using a pulse to represent a single event hit on CPs, the SET analysis model is established and the characteristics of SET generation and propagation in PLLs are revealed. An analysis of single event transients in PLLs demonstrates that the settling time of the voltage-controlled oscillators (VCOs) control voltage after a single event strike is strongly dependent on the peak control voltage deviation, the SET pulse width, and the settling time constant. And the peak control voltage disturbance decreases with the SET strength or the filter resistance. Furthermore, the analysis in the proposed PLL model is confirmed by simulation results using MATLAB and HSPICE,respectively.