一种用于3.125Gbps高速互连的低功耗模拟均衡器

设计了适用于多种高速通信指标(USB2.0, PCI-E,Rapid IO)的CMOS模拟均衡器. 提出的电路结构可以覆盖1Gbps到3.125Gbps的频率范围,频率的调节是通过调整均衡器的零极点位置而获得的,所以这个电路可以根据信道特性的不同来相应的调整系统的频率响应。为了平衡内部结点的寄生电容,对称开关分别用在了两个差分信号路径上以保持两个差分信号有相同的负载。该芯片采用0.13um CMOS 1P8M工艺,实际的面积为0.49 × 0.5 mm2。测试表明,该芯片经过3m RG-58同轴线缆和50cm 印制电路板走线之后,可以稳定的传输3.125Gbps的伪随机码流。芯片的整体功耗大约为14.4mW.     

A low power CMOS 3.3 Gbps continuous-time adaptive equalizer for serial link

This paper describes using a high-speed continuous-time analog adaptive equalizer as the front-end of a receiver for a high-speed serial interface,which is compliant with many serial communication specifications such as USB2.0,PCI-E2.0 and Rapid 10.The low and high frequency loops are merged to decrease the effect of delay between the two paths,in addition,the infinite input impedance facilitates the cascade stages in order to improve the high frequency boosting gain.The implemented circuit architecture could facilitate the wide frequency range from 1 to 3.3 Gbps with different length FR4-PCB traces,which brings as much as 25 dB loss.The replica control circuits are injected to provide a convenient way to regulate common-mode voltage for full differential operation.In addition,AC coupling is adopted to suppress the common input from the forward stage.A prototype chip was fabricated in 0.18-μm 1P6M mixed-signal CMOS technology.The actual area is 0.6×0.57 mm~2 and the analog equalizer operates up to 3.3 Gbps over FR4-PCB trace with 25 dB loss.The overall power dissipation is approximately 23.4 mW.     

一种用于3.3Gbps低功耗高速互连的连续时间自适应模拟均衡器*

设计了适用于多种高速通信指标(USB2.0, PCI-E,Rapid IO)的CMOS模拟均器。通过合并低频和高频支路以降低两个支路的延迟效应,同时均衡滤波器具有比较大的输入阻抗,这有利于通过级联方式来进一步提高高频增益。本文所实现的电路结构在25dB的PCB线路衰减条件下,能够均衡频率范围从1Gbps到3.3Gbps的信号。偏置电路采用复制电路技术,有利于方便的调整主要工作模块的直流工作点。为了抑制前级输出共模对后级电路的影响,在信号的输入端引入了交流耦合。该芯片在0.18um 1P6M工艺下进行了流片验证,整体芯片面积为0.6 x 0.57 mm². 测试结果显示,该模拟均衡器能够在25dB FR4 PCB信道衰减下,对速率为3.3Gbps的信号实现自适应均衡,整体功耗大约为23.4mw.     

An edge-based dual adaptive decision feedback equalizer for Gbps serial links

This paper presents an adaptive edge-DFE for 2PAM Gbps serial links. The optimal tap coefficients of the DFE are obtained by minimizing the jitter of received data. Reference voltage for generating DFE error signal is also obtained iteratively using an edge-DFE like algorithm. Issues critical to the proposed adaptive edge-DFE are examined in detail. The effectiveness of the proposed adaptive edge-DFE has been validated using a 5 Gbps serial link designed in a 65 nm 1.2 V CMOS technology. The effect of PVT (process, voltage, and temperature) variations on the performance of the proposed DFE has also been investigated. Simulation results demonstrate that the DFE is capable of opening completely closed data eyes when the DFE is absent. Equalized data have 55 % vertical-opening and 86.5 % horizontal eye-opening with 25 ns adaption time.     

一种用于电流型电化学传感器的CMOS模拟前端芯片

本文提出了一种用于电流型电化学传感器的CMOS模拟前端芯片,芯片具有高度可编程性,其内部集成了可通过I2C接口总线与外部控制芯片通信的可配置数字模块电路。结合incremental型sigma-delta模数转换器与数字域相关双采样技术,提出并实现了一种新的两次采样的系统架构。该芯片基于华虹宏力0.18μm标准CMOS工艺流片,消耗芯片面积为1.3 mm × 1.9 mm,测试结果表明：该芯片16位数字输出具有高精度,高线性度特性,可检测溶液中磷酸根离子浓度的精度为0.01 mg/L。     

使用预失真技术的全集成线性CMOS功率放大器

本文使用了模拟预失真技术设计了用于2.5 GHz的m-WiMAX发射机系统的基于转换器的CMOS功率放大器,功率级和驱动级的三次谐波可以在特定功率范围内相互抵消。使用标准0.18μmCMOS工艺设计的两级功放在1 dB压缩点处的功率为27.5 dBm,功率增加效率为27%。在20.5 dBm的平均功率下可以满足功率谱的要求,EVM为5.5%。测试结果表明,与传统的使用三阶跨导零点偏置技术设计的功放相比,该功放具有良好的线性度和效率。     

A highly linear fully integrated CMOS power amplifier with an analog predistortion technique

A transformer-based CMOS power amplifier（PA） is linearized using an analog predistortion technique for a 2.5-GHz m-WiMAX transmitter.The third harmonic of the power stage and driver stage can be cancelled out in a specific power region.The two-stage PA fabricated in a standard 0.18μm CMOS process delivers 27.5 dBm with 27%PAE at the 1-dB compression point(P_1dB) and offers 21 dB gain.The PA achieves 5.5%EVM and meets the spectrum mask at 20.5 dBm average power.Another conventional PA with a zero-cross-point of g_m3 bias is also fabricated and compared to prove its good linearity and efficiency.     

A power-efficient 2-dimensional on-chip eye-opening monitor for Gbps serial links

This paper investigates the drawbacks of widely used rectangular eye-opening monitors (EOMs) and proposes a new power-efficient half hexagon EOM for Gbps serial links. The proposed EOM outperforms rectangular EOMs by providing a better control of data jitter at the edge of data eyes and by eliminating unnecessary errors flagged by rectangular EOMs. The effectiveness of the proposed EOM is evaluated using a serial link implemented in IBM 130 nm 1.2 V CMOS technology. For purpose of comparison, rectangular EOMs with the same data link are also designed and evaluated. The data links are analyzed using Spectre from Cadence Design Systems with BSIM 4 device models. Simulation results demonstrate that the proposed EOM provides a better detection of the violation of the minimum eye-opening mask over temperature range ?20 to 80 °C and at all process corners as compared with rectangular EOM, with 50 % reduction in power and silicon consumption.     

CMOS mm-wave transceivers for Gbps wireless communication

The challenges in the design of CMOS millimeter-wave (mm-wave) transceiver for Gbps wireless communication are discussed. To support the Gbps data rate, the link bandwidth of the receiver/transmitter must be wide enough, which puts a lot of pressure on the mm-wave front-end as well as on the baseband circuit. This paper discusses the effects of the limited link bandwidth on the transceiver system performance and overviews the bandwidth expansion techniques for mm-wave amplifiers and IF programmable gain amplifier. Furthermore, dual-mode power amplifier (PA) and self-healing technique are introduced to improve the PA''s average efficiency and to deal with the process, voltage, and temperature variation issue, respectively. Several fully-integrated CMOS mm-wave transceivers are also presented to give a short overview on the state-of-the-art mm-wave transceivers.     

Single-pair bulk-driven CMOS input stage: A compact low-voltage analog cell for scaled technologies

Bulk-driven MOS transistors lead to a compact low-voltage/low-power input stage implementation. This paper illustrates the rail-to-rail capability of a single-pair bulk-driven CMOS input stage operated from an extremely low supply voltage. A composite input stage is also introduced to point out some limitations inherent in multiple-pair input stages and carry out performance comparison, based on experimental data obtained in standard 0.35 μm CMOS technology. The performance achieved by the single-pair bulk-driven input stage can be readily extended to a nanoscale process, as lower supply voltages in scaled technologies are expected. Measurements demonstrate the rail-to-rail suitability of the single-pair input stage and show intrinsic advantages of this approach in some amplifier features, such as linearity and common-mode rejection ratio, as compared to the case of the composite solution.     

A 5 Gb/s CMOS adaptive equalizer for serial link

A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13μm CMOS process.The circuit consists of the combination of equalizer amplifier,limiter amplifier and adaptation loop.The adaptive algorithm exploits both the low frequency gain loop and the equalizer loop to minimize the inter-symbol interference (ISI) for a variety of cable characteristics.In addition,an offset cancellation loop is used to alleviate the offset influence of the signal path.The adaptive equalizer core occupies an area of 0.3567 mm2 and consumes a power consumption of 81.7 mW with 1.8 V power supply.Experiment results demonstrate that the equalizer could compensate for a designed cable loss with 0.23 UI peak-to-peak jitter.     

Design method for CMOS current-source modes power amplifiers based on PAE optimization

An efficient method for CMOS current-source modes (A, B, AB, C classes) Power Amplifier (PA) design for low-power applications is presented. This method allows to set the conduction angle α and the transistor size W/L in order to maximize the PAE. In a first step, an analytical approach, built from a simple transistor model, gives a first approximation of the optimum α and W/L. In a second step and from the analytical results, a simulation approach, illustrated with a 0.28μm CMOS foundry design-kit, allows to precisely determine the optimum conduction angle and the transistor size. A PA designed with this method at 2.45 GHz for a class 2 Bluetooth application shows a 41% PAE and a surface consumption of 0.28 mm² for an output power of 4 dBm.     

A New CMOS Current-Mode Multiplexer for l0 Gbps Serial Links

This paper presents an in-depth study of the pros and cons of voltage-mode multiplexers for Gbps serial links and exploits the advantages of multiplexing in current domain. In addition, it proposes a new fully differential CMOS current-mode multiplexer where a high multiplexing speed is achieved by multiplexing at a low-impedance node. Multiplexing speed is further improved by inductive shunt peaking with active inductors. The differential configuration of the multiplexer minimizes the effect of common-mode disturbances, particularly those coupled from the power and ground rails. The flow of the output currents in the opposite directions minimizes the effect of electro-magnetic interference from channels, making the multiplexer particularly attractive for high-speed data transmission over long interconnects and printed-circuit-board (PCB) traces. The proposed multiplexer draws a constant current from the supply voltage, thereby minimizing both switching noise and noise injected to the substrate. A fully differential CMOS current-mode 8-to-l multiplexer has been implemented in TSMC’s 1.8 V 0.18 μm CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3.3v device models. Simulation results demonstrate that the multiplexer offers sufficiently large eye-opening when multiplexed at 10 Gbps.Jean Jiang received the B.Eng. degree in Electrical Engineering from Wuhan University of Technology, Wuhan, China in 1995. From 1999 to 2001, she worked for Ericsson Global IT Services where she was a technical staff to maintain computer networks. Since 2002, she has been a research assistant with the System-on-Chip research lab of Ryerson University. She is currently a M.A.Sc candidate under the supervision of Dr. Fei Yuan in the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Canada. Her research interests are in analog CMOS circuit design for high-speed data communications. She was awarded the Ontario Graduate Scholarship (OGS) in 2003–2005 for academic excellence.Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the MASc. degree in chemical engineering and PhD. degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively.During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Canada. During 1989–1994, he worked for Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer. Since July 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book “Computer Methods for Analysis of Mixed-Mode Switching Circuits” (Kluwer Academic Publishers, 2004, with Ajoy Opal). Dr. Yuan received an “Excellence of Teaching” award from Changzhou Institute of Technology in 1988, a post-graduate scholarship from Natural Science and Engineering Research Council (NSERC) of Canada during 1997–1998. He is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada.     

A Methodology for Long Time Constant Log-Domain Filters in CMOS

A simple methodology for implementation of low-order, current-mode, log-domain filters in CMOS technology is presented. The key transistors in the circuit are operated in weak inversion and in contrast with previous approaches may pass into the triode regime. The concept is particularly suited to implementation in silicon-on-insulator technology, because dielectric isolation of the transistors eliminates leakage currents, and because influence of the body effect on circuit function is limited. Very long time constants, on the order of 1 s or more, are obtainable. A simple elaboration of the basic unit circuit allows the time constant to be controlled by a bias current.Patrick Shoemaker received the B.A., M.S., and Ph.D. degrees in Bioengineering from the University of California, San Diego. From 1984 to 1998 he was an engineer with the Space and Naval Warfare Systems Center in San Diego, where he worked on modeling and implementation of artificial neural networks, and analog and mixed-signal circuit design. Since 1998 he has been with Tanner Research in Pasadena, California, where his work has focused on biological information processing (in particular, insect vision) and on biomimetic analog integrated circuits. Dr. Shoemaker is a member of the IEEE and the International Neural Network Society.     

A High Speed, Low Voltage CMOS Offset Comparator

A high speed, low voltage offset comparator is presented. No common mode tracking circuit is used and the offset is added without compromising the high input impedance nature of the circuit. The circuit operates at 480 Mbps with 3.0–3.6 V and 1.6–2.0 V supplies and –40 to 125°C temperature range on a typical 0.5 m technology.     

A modified Park-Kim voltage-controlled ring oscillator for multi-Gbps serial links

This paper proposes a new multi-stage CMOS voltage-controlled ring VCO called modified Park-Kim ring VCO for multi-Gbps serial links. An in-depth comparative study of pros and cons of Park-Kim VCO and the modified Park-Kim VCO with both single and dual delay paths is given. We show that the modified Park-Kim VCO offers an improved oscillation frequency, large output voltage swing, comparable frequency tuning range and phase noise as compared with Park-Kim VCO proposed in [1, 2]. We further show that although the modified Park-Kim VCO with single delay path and that with dual delay path offer comparable oscillation frequencies when the number of stages of the VCOs is high, the former provides a large frequency tuning range and reduced circuit complexity. To verify performance improvement, both Park-Kim VCOs and the modified Park-Kim VCOs are implemented in TSMC’s-0.18 μm, 1.8 V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3.3 device models. Simulation results are presented.     

一种适用于便携式多模式全球卫星导航系统接收机的低功耗宽带频率合成器设计

本文提出了一种适用于便携式多模式全球卫星导航系统（GNSS）接收机的低功耗宽带频率合成器,并分析了GNSS接收机频率合成器的设计要点。该频率合成器通过采用具有调谐曲线补偿功能的单一VCO实现了较宽的频率范围,同时具有较低的功耗和好的相位噪声性能。该频率合成器在CMOS 0.18um 1P6M工艺上流片验证成功。测试表明,带内相位噪声小于-95dBc@200KHz,频率调谐范围为1.47-1.83GHz,而整个电路面积仅为0.55mm2,整个频率合成器功耗小于11.2mw。     

A low power wide-band CMOS PLL frequency synthesizer for portable hybrid GNSS receiver

The design consideration and implementation of a CMOS frequency synthesizer for the portable hybrid global navigation satellite system are presented. The large tuning range is achieved by tuning curve compensation using an improved VCO resonant tank, which reduces the power consumption and obtains better phase noise performance.The circuit is validated by simulations and fabricated in a standard 0.18μm 1P6M CMOS process. Close-loop phase noise measured is lower than -95 dBc at 200 kHz offset while the measured tuning range is 21.5% from 1.47 to 1.83 GHz. The proposed synthesizer including source coupled logic prescaler consumes 6.2 mA current from 1.8 V supply.The whole silicon required is only 0.53 mm~2.     

A new CMOS class AB serial link transmitter with a low supply voltage sensitivity

This paper presents a new class AB transmitter with a low supply voltage/ground bouncing sensitivity for 10 Gb/s serial links. The low sensitivity of the output current to supply voltage fluctuation and ground bouncing is achieved by operating the system in a rail-to-rail swing mode. High data rates are obtained by multiplexing at low-impedance nodes and inductive shunt peaking with active inductors. The fully differential configuration and bipolar signaling of the transmitter minimize the effect of both common-mode disturbances and electro-magnetic interferences exerted from channels to neighboring devices. The class AB operation of the transmitter minimizes its static power consumption. The proposed transmitter is implemented in a 1.2 V 0.13μm CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3v3 device models. Both pre and post-layout simulation results demonstrate that the transmitter conveys a sufficiently large differential output current that is insensitive to supply voltage fluctuation and ground bouncing at 10 Gb/s. Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the M.A.Sc. degree in chemical engineering, and Ph.D. degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively. During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Ontario, Canada, and Lambton College of Applied Arts and Technology, Sarnia, Ontario, Canada. He was with Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer during 1989–1994. Since 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book Computer Methods for Analysis of Mixed-Mode Switching Circuits (Springer-Verlag, 2004, with Ajoy Opal). Dr. Yuan received the Ryerson Research Chair award from Ryerson University in Jan. 2005, the Research Excellence Award from the Faculty of Engineering and Applied Science of Ryerson University in 2004, the post-graduate scholarship from Natural Science and Engineering Research Council of Canada during 1997–1998, and the Teaching Excellence Award from Changzhou Institute of Technology in 1988. Dr. Yuan is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada. Minghai Li received the B.Eng. (96) and M.A.Sc (06) degrees from North University of China and Ryerson University, Toronto, Ontario, Canada, respectively, both in Electrical and Computer Engineering. During 1996–2001, he was with Motorola Semiconductor (China) as a MCU product engineer. He was involved with MCU new product design, simulation, and test program development. He was a research assistant and a M.A.Sc student with the Microsystems Research Laboratory in the Department of Electrical and Computer Engineering at Ryerson University. He is now with Micron Technology Inc., Boise, Idaho, USA as a design engineer. His research interest is in the design of CMOS mixed-signal circuits for high-speed data transmission, including multiplexer, driver, pre-emphasis, and VCOs.