A low noise high efficiency buck DC-DC converter with sigma-delta modulation

Some research efforts to improve the efficiency and noise performance of buck DC-DC converters are explored.A carefully designed power MOSFET driver,including a dead time controller,discontinuous current mode(DCM) controller and gate width controller,is proposed to improve efficiency.Instead of PWM modulation, sigma-delta modulation is introduced into the feedback loop of the converter to move out the clock-referred harmonic spike.The proposed converter has been designed and fabricated by a 0.35μm CMOS process.Measured results show that the peak efficiency of the converter can reach 93%and sigma-delta modulation suppresses the harmonic spike by 30 dB over PWM modulation.     

一种基于sigma-delta调制的高效率低噪声降压式直流变换器

本论文在提高开关电源效率和降低噪声方面做了一些工作。在效率方面,提出了一个包含死区时间控制,断流模式控制以及栅宽调制功能的高效率功率管驱动电路。在控制回路中采用sigma-delta调制取代传统的PWM调制,降低了开关电源输出中与时钟有关的谐波噪声。本文在 0.35um CMOS工艺条件下实现了一个基于二阶sigma-delta调制的高效率低噪声DC-DC变换器。测试结果表明,此变换器能够达到93%的峰值效率,并且谐波噪声可以比使用PWM调制时低30dB。     

Dithering Skip Modulation, Width and Dead Time Controllers in Highly Efficient DC-DC Converters for System-On-Chip Applications

This paper proposes temperature-independent load sensor (LS), optimum width controller (OWC), optimum dead-time controller (ODC), and tri-mode operation to achieve high efficiency over an ultra-wide-load range. Higher power efficiency and wider loading current range require rethinking the control method for DC-DC converters. Therefore, a highly efficient tri-mode DC-DC converter is invented in this paper for system-on-chip (SoC) applications, which is switched to sleeping mode at very light load condition or to high-speed mode at heavy load condition. The efficiency improvement is upgraded by inserting new proposed dithering skip modulation (DSM) between conventional pulse-width modulation (PWM) and pulse-frequency modulation (PFM). In other words, an efficiency-improving DSM operation raises the efficiency drop because of transition from PWM to PFM. Importantly, DSM mode can dynamically skip the number of gate driving pulses, which is inverse proportional to load current. Simplistically and qualitatively stated, the novel load sensor automatically selects optimum modulation method and power MOSFET width to achieve high efficiency over a wide load range. Moreover, optimum power MOSFET turn-on and turn-off delays in synchronous rectifiers and reduced ground bounce can save much switching loss by current-mode dead-time controller. Experimental results show the tri-mode operation can have high efficiency about 90% over a wide load current range from 3 to 500 mA. Owing to the effective mitigation of the switching loss contributed by optimum power MOSFET width and reduction of conduction loss contributed by optimum dead-times, the novel width and dead-time controllers achieve high efficiency about 95% at heavy load condition and maintain the highly efficient performance to very light load current about 0.1 mA.     

采用分段式自适应PWM/PFM调制的Buck型DC-DC转换器设计北大核心

为了在轻重负载条件下获得更高的转换效率，采用分段式结构和导通电阻更小的NMOS作为输入级，并采用PWM/PFM双调制方式，设计了一种Buck型DC-DC转换器。为解决PWM/PFM调制信号切换问题，采用零电流检测方式进行切换。利用断续导通模式(DCM)和连续导通模式(CCM)下端NMOS管导通时电感电压的不同，检测下端NMOS在导通时电感电压大于零的周期。当电感电压大于零的周期大于2时，则处于DCM模式并自动采用PFM调制模式，关闭一部分功率管以减小开关频率和功率管寄生电容，优化轻载效率；反之则处于CCM模式并采用PWM调制。仿真结果表明，在负载电流10～1 000 mA范围内，该电路可以在两种调制模式平稳切换，在800 mA时峰值效率可提升到96%以上。     

Design of high efficiency dual-mode buck DC-DC converter

A buck DC-DC switching regulator with high efficiency is implemented by automatically altering the modulation mode according to load current,and it can operate with an input range of 4.5 to 30 V.At light load current,the converter operates in skip mode.The converter enters PWM mode operation with increasing load current.It reduces the switching loss at light load and standby state,which results in prolonging battery lifetime and stand-by time.Meanwhile, externally adjustable soft-start minimizes the inru...     

一种基于自适应峰值电流检测的模式切换电路北大核心

在降压转换器中，为了在不同的负载情况下获得高效率，常采用的方法是在重载时使用脉冲宽度调制(PWM),在轻载时使用脉冲频率调制(PFM),因此需要模式切换信号去控制整个降压转换器的工作状态，同时模式切换信号也可以用于自适应改变功率级电路中的功率管栅宽，减小功率管的栅极电容，提高整体电路的效率。文章设计了一个自适应峰值电流模式切换电路，用于产生模式切换信号，其原理是监控峰值电流的变化，产生峰值电压，将峰值电压与参考电压进行比较，得到模式切换信号，以决定降压转换器是采用PFM模式还是PWM模式。仿真结果表明，在负载电流0.5～500 mA范围内，该电路可以在两种调制模式之间平稳切换，其峰值效率可提升到94%以上。     

一种具有750mA输出电流,双模式PWM/PFM控制的高效率直流-直流降压转换器

提出了一种输出电流可达750mA,脉宽调制（PWM）和变频调制（PFM）双模式控制的,高效率、高稳定性直流-直流降压转换器.该转换器在负载电流大于80mA时,采用开关频率为1MHz的PWM工作模式;在负载电流小于80mA时,采用开关频率减小和静态电流降低的PFM工作模式,实现了在整个负载电流变化范围（0.02~750mA）内,转换器均保持高效率.而且采用一种快速响应的电压模式控制结构,达到了优异的线性和负载调整特性.芯片采用CSMC公司0.5μm CMOS 2P3M混合信号工艺物理实现.测试结果表明,该电路可根据负载的变化在PWM和PFM模式下自动切换.最大转换效率达96.5%;当负载电流为0.02mA时,转换效率大于55%.该芯片特别适合电池供电的移动系统使用.     

Analysis of High-Frequency IGBT Soft Switching Buck Converter With Saturable Inductors

In this paper, a high switching frequency buck converter using insulated gate bipolar transistors (IGBTs) is presented. This was done by using an auxiliary branch made of an IGBT of the same type as the one used for the main switch and saturable inductors. The proposed topology allows both switches to be fully soft switched to keep the efficiency high over a wide load range. Because of its topology the open loop behavior of the converter can be unstable. A detailed small signal analysis is presented to explain this behavior and as a basis for the synthesis of a closed loop controller. Experimental measurements on a laboratory prototype demonstrated the accuracy of the small signal analysis and validated the operation of the auxiliary network. The resulting efficiency is around 92% over a 200 to 800W output power range and at a 80-kHz switching frequency     

一种提高单电感双输出升/降压型转换器轻载效率的设计策略

为了提高单电感双输出升/降压型直流-直流转换器在轻载下的效率,设计实现了适用于不同转换条件的非连续导通模式(DCM)功能和脉冲频率调制(PFM)控制。前者降低了电感电流的均方根值,减少了导通损耗;后者降低了开关频率,减少了开关损耗。详细分析了在PFM控制下转换器的驱动能力、电感电流纹波和输出电压纹波之间相互制约的关系,并采取了一种可以由两路任意升/降压输出灵活复用的自适应导通时间控制方法。经0.25μm 2P4M CMOS混合信号工艺流片验证,测试结果显示DCM和PFM时序与设计方案吻合,各种转换条件下输出电压纹波在40~70 mV。通过比较发现,对轻载效率的提升可以达到30%以上。     

Designing a compact soft-start scheme for voltage-mode DC-DC switching converters

In this paper, a compact soft-start scheme is proposed and successfully applied to typical voltage-mode DC-DC switching converters. The adaptive current limitation implemented through DAC control will largely reduce the overshoot voltage under a wide range of output current. Proven experimentally by a buck converter implemented in a 0.5 μm CMOS technology, the post-simulation results show that when the converter starts up, the maximum overshoot (2.7% at I_LOAD=0 A) by the proposed soft-start scheme is less than that with the conventional scheme by 5% under the same condition. The start-up time can be adaptively adjustable depending on load current and the maximum start-up time is around 760 μs with 22 μF output capacitor. The circuits which realize the soft-start scheme can also be fully integrated into the control chip of DC-DC switching converter resulting in low cost.     

An automatic load-adaptive switching frequency selection technique for improving the light-load efficiency of a buck converter

A load-adaptive automatic switching frequency selection scheme is proposed to improve the power efficiency of a switching buck converter at light load condition. The buck converter operates in the continuous-conduction mode for heavy loading and the switching frequency is fixed at its maximum value. For light loading, the buck converter operates in the discontinuous-conduction mode and its switching frequency is automatically selected among a pre-defined set of frequencies according to the amount of the load current. The load current can be sensed indirectly by monitoring the on-time of power transistor because it is a function of the load current. With the proposed load-adaptive automatic switching frequency selection circuit, the power efficiency of a buck converter implemented in a 0.35-μm 2P4M BCDMOS technology is improved by 24.0-% when the load current load is 10-mA.     

A digitally controlled PWM/PSM dual-mode DC/DC converter

A digitally controlled pulse width modulation/pulse skip modulation(PWM/PSM) dual-mode buck DC/DC converter is proposed.Its operation mode can be automatically chosen as continuous conduction mode (CCM) or discontinuous conduction mode(DCM).The converter works in PSM at DCM and in 2 MHz PWM at CCM.Switching loss is reduced at a light load by skipping cycles.Thus high conversion efficiency is realized in a wide load current.The implementations of PWM control blocks,such as the ADC,the digital pulse width modulator(DPWM) and the loop compensator,and PSM control blocks are described in detail.The parameters of the loop compensator can be programmed for different external component values and switching frequencies, which is much more flexible than its analog rivals.The chip is manufactured in 0.13μm CMOS technology and the chip area is 1.21 mm~2.Experimental results show that the conversion efficiency is high,being 90%at 200 mA and 67%at 20 mA.Meanwhile,the measured load step response shows that the proposed dual-mode converter has good stability.     

A high efficiency, soft switching DC-DC converter with adaptive current-ripple control for portable applications

A novel control scheme for improving the power efficiency of low-voltage dc-dc converters for battery-powered, portable applications is presented. In such applications, light-load efficiency is crucial for extending battery life, since mobile devices operate in stand-by mode for most of the time. The proposed technique adaptively reduces the inductor current ripple with decreasing load current while soft switching the converter to also reduce switching losses, thereby significantly improving light-load efficiency and therefore extending the operation life of battery-powered devices. A load-dependent, mode-hopping strategy is employed to maintain high efficiency over a wide load range. Hysteretic (sliding-mode) control with user programmable hysteresis is implemented to adaptively regulate the current ripple and therefore optimize conduction and switching losses. Experimental results show that for a 1-A, 5- to 1.8-V buck regulator, the proposed technique achieved 5% power efficiency improvement (from 72% to 77%) at 100 mA of load current and a 1.5% improvement (from 84% to 85.5%) at 300 mA, which constitute light-load efficiency improvements, when compared to the best reported, state-of-the-art techniques. As a result, the battery life in a typical digital signal processing microprocessor application is improved by 7%, which demonstrates the effectiveness of the proposed solution.     

An Accurate, Low-Voltage, CMOS Switching Power Supply With Adaptive On-Time Pulse-Frequency Modulation (PFM) Control

Integrated switching power supplies with multimode control are gaining popularity in state-of-the-art portable applications like cellular phones, personal digital assistants (PDAs), etc., because of their ability to adapt to various loading conditions and therefore achieve high efficiency over a wide load-current range, which is critical for extended battery life. Constant-frequency, pulsewidth modulated (PWM) switching converters, for instance, have poor light-load efficiencies because of higher switching losses while pulse-frequency modulation (PFM) control in discontinuous-conduction mode (DCM) is more efficient at light loads because the switching frequency and associated switching losses are scaled down with load current. This paper presents the design and integrated circuit prototype results of an 83% power efficient 0.5-V 50-mA CMOS PFM buck (step-down) dc-dc converter with a novel adaptive on-time scheme that generates a 27-mV output ripple voltage from a 1.4- to 4.2-V input supply (battery-compatible range). The output ripple voltage variation and steady-state accuracy of the proposed supply was 5 mV (22-27 mV) and 0.6% whereas its constant on-time counterpart was 45 mV (10-55 mV) and 3.6%, respectively. The proposed control scheme provides an accurate power supply while achieving 2%-10% higher power efficiency than conventional fixed on-time schemes with little circuit complexity added, which is critical during light-loading conditions, where quiescent current plays a pivotal role in determining efficiency and battery-life performance     

A high-efficiency,low-noise power solution for a dual-channel GNSS RF receiver

A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented.The power solution involves a DC-DC buck converter and a followed low-dropout regulator(LDO).The pulsewidth -modulation(PWM) control method is adopted for better noise performance.An improved low-power highfrequency PWM control circuit is proposed,which halves the average quiescent current of the buck converter to 80μA by periodically shutting down the OTA.The size of the output stage has also been optimized to achieve high efficiency under a light load condition.In addition,a novel soft-start circuit based on a current limiter has been implemented to avoid inrush current.Fabricated with commercial 180-nm CMOS technology,the DC-DC converter achieves a peak efficiency of 93.1%under a 2 MHz working frequency.The whole receiver consumes only 20.2 mA from a 3.3 V power supply and has a noise figure of 2.5 dB.     

高性能PWM型DC-DC升压变换器研究

设计了一种单片集成PWM型电流模式升压变换器,芯片内部集成了耐压22V的DMOS功率开关管,开关频率为1.6MHz,采用1.5μmBCD工艺实现。芯片具有很宽的输入电压(2.7~14V)、高效率(85%)、低关断电流、快速暂态响应和低功耗等特性,适宜于用作便携式设备的电源管理,也可作为IP核,嵌入同种工艺下的其它芯片。文中除了对芯片设计方法、思路及主要电路模块结构的设计方案进行讨论外,还提出了减小单片集成开关电源噪声的措施。     

用于降压型DC-DC转换器的死区时间控制电路

介绍了降压型DC-DC转换器的死区时间产生原理,给出一种死区时间控制电路.它通过采样电感中的电流,动态地调节死区延时,减小体二极管的导通时间,并且可抑制振铃现象的产生.在Cadence环境下对电路进行整体仿真.结果表明,在1 MHz频率下,死区时间能够随负载电流的变化而改变;体二极管的导通时间减小到1.5～2.5 ns,提高了系统的效率.     

一种多相DC-DC数字控制器的设计

分析了多相DC-DC变换器的均流环路小信号动态特性以及极限环振荡条件,提出一种基于平均电流的数字均流技术,并据此实现了一种多相DC-DC数字控制器。采用基于同步设计的均流控制电路和数字脉宽调制器实现电流均衡和相位交错。该多相DC-DC数字控制器芯片基于0.18μm CMOS工艺设计。仿真结果表明,在10~20 A阶跃负载电流下,输出过冲/下冲电压在20 mV以内,开关频率在0.5 MHz~2 MHz范围内可调整,均流误差从20.8%减小到5%以下。     

具有快速动态响应的高稳定性电流型降压DC-DC转换器

提出了一种高稳定性的电流型DC-DC转换器.首先应用一种新型的电流型转换器的模型推导了控制环路的增益表达式,在分析其环路增益的基础上,提出了一种新颖的控制环路频率补偿的方法,从而使转换器的稳定性不受负载电流和电源电压变化的影响.其次应用这种新的频率补偿方法,使用0.5μm-CMOS工艺设计了一种电流模式的降压型转换器.仿真结果表明,该稳压器具有高度的稳定特性,其稳定性与负载和电源电压无关.并且由于这种新的频率补偿为环路提供了极高的带宽,所以该转换器具有优异的动态响应.其提供的全负载瞬态响应的建立时间小于5μs,过冲电压小于30mV.     

基于数字PID补偿的降压型DC-DC控制器

设计了一个基于数字PID控制,可为低压系统提供稳定电源的多相位降压型DC-DC控制电路,包括flash ADC、数字PID控制器;并设计了一种新的基于延时单元/计数器的数字PWM电路,实现了一个降压型控制器。电路使用3.3 V CMOS工艺设计,芯片面积为0.16 mm2,输入电压3 V,输出电压1.25 V,负载电流最大800 mA,纹波小于10 mV,开关频率1 MHz,效率最高达到90%。