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1.
A Wideband CMOS Low Noise Amplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner 总被引:1,自引:0,他引:1
《Solid-State Circuits, IEEE Journal of》2009,44(3):686-698
2.
This paper proposes a high‐efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current‐mode transformer‐based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18‐μm RF‐CMOS process with a supply voltage of 3.3 V. The measured gain, P1dB, and efficiency at P1dB are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25‐dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained. 相似文献
3.
A capacitance-compensation technique for improved linearity in CMOS class-AB power amplifiers 总被引:2,自引:0,他引:2
Chengzhou Wang Vaidyanathan M. Larson L.E. 《Solid-State Circuits, IEEE Journal of》2004,39(11):1927-1937
A nonlinear capacitance-compensation technique is developed to help improve the linearity of CMOS class-AB power amplifiers. The method involves placing a PMOS device alongside the NMOS device that works as the amplifying unit, such that the overall capacitance seen at the amplifier input is a constant, thus improving linearity. The technique is developed with the help of computer simulations and Volterra analysis. A prototype two-stage amplifier employing the scheme is fabricated using a 0.5-/spl mu/m CMOS process, and the measurements show that an improvement of approximately 8 dB in both two-tone intermodulation distortion (IM3) and adjacent-channel leakage power (ACP1) is obtained for a wide range of output power. The linearized amplifier exhibits an ACP1 of -35 dBc at the designed output power of 24 dBm, with a power-added efficiency of 29% and a gain of 23.9 dB, demonstrating the potential utility of the design approach for 3GPP WCDMA applications. 相似文献
4.
Wenchang Huang Sanchez-Sinencio E. 《IEEE transactions on circuits and systems. I, Regular papers》2006,53(7):1433-1447
An enhanced configuration for a linearized MOS operational transconductance amplifier (OTA) is proposed. The proposed fully differential OTA circuit is based on resistive source degeneration and an improved adaptive biasing technique. It is robust to process variation, which has not been fully shown in previously reported linearization techniques. Detailed harmonic distortion analysis demonstrating the robustness of the proposed OTA is introduced. The transconductance gain is tunable from 160 to 340 /spl mu/S with a third-order intermodulation (IM3) below -70 dB at 26 MHz. As an application, a 26-MHz second-order low-pass filter fabricated in TSMC 0.35-/spl mu/m CMOS technology with a power supply of 3.3 V is presented. The measured IM3 with an input voltage of 1.4 Vpp is below - 65 dB for the entire filter pass-band, and the input referred noise density is 156nV//spl radic/Hz. The cutoff frequency of the filter is tunable in the range of 13-26 MHz. Theoretical and experimental results are in good agreement. 相似文献
5.
介绍了一种利用宽带输入匹配网络调整峰值功放输出电流,改善Doherty 功放负载调制效果和带内
效率的设计方法。理论分析表明,Doherty功放中峰值功放C 类偏置情况下带来的带内不一致开启特性会影响输出
电流和负载调制效果。通过引入宽带输入匹配网络,能有效改善它的开启不一致性。为验证分析结果设计了具有
宽带(采用简易实频技术)和窄带两种不同输入匹配网络,用于2.15GHz 频段LTE-A 的Doherty功放。仿真和测试
结果表明,功放的输出功率超过49dBm,在7dB 回退功率处,宽带输入匹配Doherty 功放的带内效率达到42% 以上,
效率波动由10%降低到2%。使用100MHz 宽带LTE-A 信号经过线性化改善后,在40dBm 输出时,宽带输入匹配网
络的Doherty功放上下边带ACLR(adjacent channel leakage ratio)指标为-45.1/-44.9dBc,效率为40.5%,均优于窄带输入匹配网络的Doherty功放。 相似文献
6.
《Solid-State Circuits, IEEE Journal of》1997,32(2):159-168
A new bandpass amplifier which performs both functions of low-noise amplifier (LNA) and bandpass filter (BPF) is proposed for the application of 900-MHz RF front-end in wireless receivers. In the proposed amplifier, the positive-feedback Q-enhancement technique is used to overcome the low-gain low-Q characteristics of the CMOS tuned amplifier. The Miller-capacitance tuning scheme is used to compensate for the process variations of center frequency. Using the high-Q bandpass amplifier in the receivers, the conventional bulky off-chip filter is not required. An experimental chip fabricated by 0.8-μm N-well double-poly-double-metal CMOS technology occupies 2.6×2.0 mm2 chip area. Under a 3 V supply voltage, the measured quality factor is tunable between 2.2 and 44. When the quality factor is tuned at Q=30, the measured center frequency of the amplifier is tunable between 869-893 MHz with power gain 17 dB, noise figure 6.0 dB, output 1 dB compression point at -30 dBm, third-order input intercept point at -14 dBm, and power dissipation 78 mW 相似文献
7.
This paper presents the design of a low-power ultra-wideband low noise amplifier in 0.18-mum CMOS technology. The inductive degeneration is applied to the conventional distributed amplifier design to reduce the broadband noise figure under low power operation condition. A common-source amplifier is cascaded to the distributed amplifier to improve the gain at high frequency and extend the bandwidth. Operated at 0.6V, the integrated UWB CMOS LNA consumes 7mW. The measured gain of the LNA is 10dB with the bandwidth from 2.7 to 9.1GHz. The input and output return loss is more than 10dB. The noise figure of the LNA varies from 3.8 to 6.9dB, with the average noise figure of 4.65dB. The low power consumption of this work leads to the excellent figure of gain-bandwidth product (GBP) per milliwatt 相似文献
8.
Li-Yuan Yang Hsin-Shu Chen Chen Y.-J.E. 《Microwave and Wireless Components Letters, IEEE》2008,18(3):197-199
This letter presents the first CMOS Doherty power amplifier (PA) fully integrated on chip. The "cascode-cascade" amplifier architecture is proposed to get rid of the bulky power splitter and facilitate the integration. The quarter wavelength transmission lines are replaced by the lumped component networks such that the whole amplifier circuit can be squeezed into the die size of 1.97 times 1.4 mm2. Fabricated in 0.18 mum CMOS technology, the 3.3 V PA achieves 12 dB power gain. The measured output power and power added efficiency (PAE) at P1 dB are more than 21 dBm and 14%, respectively. The PAE at 7 dB back-off from P1 dB is above 10% and the PAE degradation is less than 29%. 相似文献
9.
10.
A high dynamic range RF variable gain amplifier (RFVGA) suitable for mobile digital television (DTV) tuners is presented. Variable gain is achieved using a capacitive attenuator and current-steering transconductance (Gm) stages, which provide high linearity with relatively low power consumption. A novel broadband input impedance matching scheme based on resistive shunt-feedback is proposed. This scheme allows the RFVGA to achieve a low noise figure. A gain control technique suitable for CMOS current-steering variable gain amplifiers is described; it features 1 dB per step resolution, independent of process and temperature variations. The chip is fabricated in six-metal 0.18mum CMOS technology and consumes 12.2mA current from 1.8V supply. The RFVGA achieves 16dB maximum gain, 33dB gain control range, a 4.3dB noise figure, and an IIP3 higher than 25dBm 相似文献
11.
《Solid-State Circuits, IEEE Journal of》2008,43(11):2404-2412
12.
13.
Jing-Lin Kuo Zuo-Min Tsai Kun-You Lin Huei Wang 《Microwave and Wireless Components Letters, IEEE》2009,19(1):45-47
A 50 to 70 GHz wideband power amplifier (PA) is developed in MS/RF 90 nm 1P9M CMOS process. This PA achieves a measured Psat of 13.8 dBm, P1 dB of 10.3 dBm, power added efficiency (PAE) of 12.6%, and linear power gain of 30 dB at 60 GHz under VDD biased at 1.8 V. When VDD is biased at 3 V, it exhibits Psat of 18 dBm, P1 dB of 12 dBm, PAE of 15%, and linear gain of 32.4 dB at 60 GHz. The MMIC PA also has a wide 3 dB bandwidth from 50 to 70 GHz, with a chip size of 0.66 times 0.5 mm2. To the author's knowledge, this PA demonstrates the highest output power, with the highest gain among the reported CMOS PAs in V-band. 相似文献
14.
S. M. Han G. Sun F. Jiang Xiao-Peng Yu X. B. Wu 《Analog Integrated Circuits and Signal Processing》2009,58(1):67-70
In this letter, a broadband area-efficient transimpedance amplifier (TIA) for optical receivers is designed using a standard
0.18 μm CMOS technology. A new shunt–shunt peaking technique is used at the input transimpedance stage, which is followed
by a gain stage and a capacitive degeneration stage. The amplifier achieves a wide bandwidth with only one inductor; hence
a smaller silicon area is maintained. The proposed TIA has a measured transimpedance gain of 50 dB Ohm and a −3 dB bandwidth
of 6.5 GHz for 0.25 pF input photodiode capacitance. It consumes DC power of 14 mW from a 1.8 V supply voltage and occupies
only 0.09 mm2 silicon area. 相似文献
15.
Chi-Hsiang Lo 《Analog Integrated Circuits and Signal Processing》2013,75(1):171-177
A proposed constant drain-source transconductor topology is designed to keep linearity at high frequency. By using the proposed operational transconductance amplifier as a building block, a fourth-order low-pass filter is realized. The filter was fabricated in 0.18 μm CMOS technology and feathers a 250 MHz cutoff frequency. The measured IM3 performance is ?36 dB at 0.6 Vpp input swing and the power consumption is 22 mW. 相似文献
16.
Hsien-Ku Chen Da-Chiang Chang Ying-Zong Juang Shey-Shi Lu 《Microwave and Wireless Components Letters, IEEE》2007,17(8):616-618
A wideband low-noise amplifier (LNA) with shunt resistive-feedback and series inductive-peaking is proposed for wideband input matching, broadband power gain and flat noise figure (NF) response. The proposed wideband LNA is implemented in 0.18-mum CMOS technology. Measured results show that power gain is greater than 10 dB and input return loss is below -10 dB from 2 to 11.5 GHz. The IIP3 is about +3 dBm, and the NF ranges from 3.1 to 4.1 dB over the band of interest. An excellent agreement between the simulated and measured results is found and attributed to less number of passive components needed in this circuit compared with previous designs. Besides, the ratio of figure-of- merit to chip size is as high as 190 (mW-1 /mm2 ) which is the best results among all previous reported CMOS-based wideband LNA. 相似文献
17.
《半导体学报》2010,31(2)
A 3-5 GHz broadband flat gain differential low noise amplifier (LNA) is designed for the impulse radio uitra-wideband (IR-UWB) system. The gain-flatten technique is adopted in this UWB LNA. Serial and shunt peaking techniques are used to achieve broadband input matching and large gain-bandwidth product (GBW). Feedback networks are introduced to further extend the bandwidth and diminish the gain fluctuations. The prototype is fabricated in the SMIC 0.18 μm RF CMOS process. Measurement results show a 3-dB gain bandwidth of 2.4-5.5 GHz with a maximum power gain of 13.2 dB. The excellent gain flatness is achieved with ±0.45 dB gain fluctuations across 3-5 GHz and the minimum noise figure (NF) is 3.2 dB over 2.5-5 GHz. This circuit also shows an excellent input matching characteristic with the measured S11 below-13 dB over 2.9-5.4 GHz. The input-referred 1-dB compression point (IPldB) is -11.7 dBm at 5 GHz. The differential circuit consumes 9.6 mA current from a supply of 1.8 V. 相似文献
18.
YunSeong Eo KwangDu Lee 《Microwave and Wireless Components Letters, IEEE》2004,14(11):504-506
A fully integrated 24-dBm complementary metal oxide semiconductor (CMOS) power amplifier (PA) for 5-GHz WLAN applications is implemented using 0.18-/spl mu/m CMOS foundry process. It consists of differential three-stage amplifiers and fully integrated input/output matching circuits. The amplifier shows a P/sub 1/ of 21.8 dBm, power added efficiency of 13%, and gain of 21 dB, respectively. The saturated output power is above 24.1 dBm. This shows the highest output power among the reported 5-GHz CMOS PAs as well as completely satisfying IEEE 802.11a transmitter back off requirement. 相似文献
19.
《Microwave Theory and Techniques》2009,57(7):1637-1646
20.
Feasibility of the cascaded single-stage distributed amplifier (CSDA) for ultra broadband amplification in complementary metal-oxide-semiconductor (CMOS) technology is investigated. A number of unique benefits gained from the CMOS CSDA over the conventional CMOS distributed amplifier structure are highlighted along with bandwidth analysis and helpful consideration. Simulated in the standard digital 0.35 μm CMOS process with realistic parasitic models, a prototype design of a four-stage CMOS CSDA provides 21 dB power gain at 5 GHz bandwidth, better than -10 dB input/output return loss and dissipates < 132 mW 相似文献