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Fabrication and Simulation of Silicon-on-Insulator Structure with Si3N4 as a Buried Insulator 总被引:2,自引:1,他引:1
In order to minimize the self-heating effect of the classic SOI devices,SOI structures with Si3N4 film as a buried insulator (SOSN) are successfully formed using epitaxial layer transfer technology for the first time.The new SOI structures are investigated with high-resolution cross-sectional transmission electron microscopy and spreading resistance profile.Experiment results show that the buried Si3N4 layer is amorphous and the new SOI material has good structural and electrical properties.The output current characteristics and temperature distribution are simulated and compared to those of standard SOI MOSFETs.Furthermore,the channel temperature and negative differential resistance are reduced during high-temperature operation,suggesting that SOSN can effectively mitigate the self-heating penalty.The new SOI device has been verified in two-dimensional device simulation and indicated that the new structures can reduce device self-heating and increase drain current of the SOI MOSFET. 相似文献
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为研究自加热效应对绝缘体上硅(SOI)MOSFET漏电流的影响,开发了一种可同时探测20 ns时瞬态漏源电流-漏源电压(Ids-Vds)特性和80μs时直流静态Ids-Vds特性的超快脉冲I-V测试方法。将被测器件栅漏短接、源体短接后串联接入超快脉冲测试系统,根据示波器在源端采集的电压脉冲的幅值计算漏电流受自加热影响的动态变化过程。选取体硅NMOSFET和SOI NMOSFET进行验证测试,并对被测器件的温度分布进行仿真,证实该方法用于自加热效应的测试是准确有效的,能为建立准确的器件模型提供数据支撑。采用该方法对2μm SOI工艺不同宽长比的NMOSFET进行测试,结果表明栅宽相同的器件,栅长越短,自加热现象越明显。 相似文献
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This paper reports a closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted (FD) SOI NMOS devices with lightly-doped drain (LDD) structure. As verified by the two-dimensional (2-D) simulation results, the analytical drain current model considering energy transport and self-heating provides an accurate prediction of the drain current behavior of the 0.25-/spl mu/m FD SOI NMOS device with and without an LDD structure. From the analytical model, with the LDD structure, the device has a smaller effective electron mobility at a low drain voltage, where lattice temperature is dominant, and a higher effective mobility at a high drain voltage, where electron temperature dominates, as compared to the non-LDD device. 相似文献
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The presence of a buried oxide layer in silicon causes enhanced self-heating in Silicon-On-Insulator (SOI) n-channel MOSFETs. The self-heating becomes more pronounced as device dimensions are reduced into the submicron regime because of increased electric field density and reduced silicon volume available for heat removal. Two-dimensional numerical simulations are used to show that self-heating manifests itself in the form of degraded drive current due to mobility reduction and premature breakdown. The heat flow equation was consistently solved with the classical semiconductor equations to study the effect of power dissipation on carrier transport. The simulated temperature increases in the channel region are shown to be in close agreement with recently measured data. Numerical simulation results also demonstrated accelerated turn-on of the parasitic bipolar transistor due to self-heating. Simulation results were used to identify scaling constraints caused by the parasitic bipolar transistor turn-on effect in SOI CMOS ULSI. For a quarter-micron n-channel SOI MOSFET, results suggest a maximum power supply of 1.8 V. In the deep submicron regime, SOI devices exhibited a negative differential resistance due to increased self-heating with drain bias voltage. Detailed comparison with bulk devices suggested significant reduction in the drain-source avalanche breakdown voltage due to increased carrier injection at the source-body junction 相似文献
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In this paper, we present an analytical one-dimensional current-voltage model for silicon-on-insulator (SOI) MOSFETs under full depletion (FD). Our model has been developed from the first principles, and it not only includes the effects of source-drain series resistances, self-heating, and parasitic BJT, which are essential to FD SOI device modeling, but also includes another important effect of substrate depletion, for the first time in the literature, which is of vital significance for FD SOI devices having small film thickness and low substrate doping. The results of the drain current obtained from our model show a much better match with the experimental data, with the maximum error being only 9.41%, which is reasonably lower than the maximum error of 15.04% produced by the model of Yu et al., and marginally better than the error of 11.5% of the model of Hu and Jang. It must be noted that, though the improvements achieved in terms of accuracy are not that significant, yet unlike other models, ours is based on a simplified one-dimensional analytical approach, which is absolutely free from iterations, and hence, there is a huge improvement in terms of computational efficiency, which establishes its practical significance. 相似文献
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A large-signal SOI MOSFET model including dynamic self-heatingbased on small-signal model parameters
A new technique for a large-signal SOI MOSFET model with self-heating is proposed, based on thermal and electrical parameters extracted by fitting a small-signal model to measured s-parameters. A thermal derivative approach is developed to calculate the thermal resistance when the isothermal dc drain conductance is extracted from small-signal fitting. The thermal resistance is used to convert the measured dc current-voltage (I-V) characteristics containing the self-heating effects to the isothermal I-V characteristics needed for the large-signal model. Large-signal pulse and sinusoidal input signals are used to verify the model by measurement, and shown to reproduce the observed large-signal behavior of the devices with great accuracy, especially when two or more thermal time constants are used 相似文献
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Sanchez F.J.G. Ortiz-Conde A. Cerdeira A. Estrada M. Flandre D. Liou J.J. 《Electron Devices, IEEE Transactions on》2002,49(1):82-88
Free-carrier mobility degradation in the channel and drain/source series resistance are two important parameters limiting the performance of MOS devices. In this paper, we present a method to extract these parameters from the drain current versus gate voltage characteristics of fully-depleted (FD) SOI MOSFETs operating in the saturation region. This method is developed based on an integration function which reduces errors associated with the extraction procedure and on the DC characteristics of MOS devices having several different channel lengths. Simulation results and measured data of FD SOI MOSFETs are used to test and verify the method developed 相似文献
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Sinitsky D. Tang S. Jangity A. Assaderaghi F. Shahidi G. Chenming Hu 《Electron Device Letters, IEEE》1998,19(9):323-325
A versatile SOI model derived from the BSIM3v3 bulk MOSFET model is capable of simulating partially and fully depleted devices with options for self-heating and floating body effects. The model can automatically switch between fully and partially depleted regimes. After refining body current models we for the first time present successful dc and transient device and circuit simulation of an SOI MOSFET technology with Leff below 0.2 μm 相似文献
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In this paper, we present a novel type of channel doping engineering, using a graded doping distribution, that improves the electrical and thermal performance of silicon-on-insulator (SOI) metal–oxide–semiconductor field effect transistors (MOSFETs), according to simulations that we have performed. The results obtained include a reduction in the self-heating effect, a reduction in leakage currents due to the suppression of short-channel effects (SCEs), and a reduction in hot-carrier degradation. We term the proposed structure a modified-channel-doping SOI (MCD-SOI) MOSFET. The main reason for the reduction in the self-heating effect is the use of a lower doping density near the drain region in comparison with conventional SOI MOSFETs with a uniform doping distribution. The most significant reason for the leakage current reduction in the MCD-SOI structure is the high potential barrier near the source region in the weak inversion state. The SCE factors, including the drain-induced barrier lowering, subthreshold swing, and threshold voltage roll-off, are improved. A highly reliable structure is achieved owing to the lower doping density near the drain region, which reduces the peak electric field and the electron temperature. 相似文献
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The silicon-on-insulator (SOI) power devices have an inherent self-heating effect, which limits their operation at high current levels. This is a consequence of the very low thermal conductivity of the thick buried oxide layer. A novel solution to reduce the self-heating effect is proposed in this paper, based on silicon-over-insulator-multilayer (SOIM) emerging technology. A significant reduction of the insulator layer thermal resistance is achieved while keeping constant the electrical behaviour of integrated power devices in comparison to the conventional SOI counterparts. The effectiveness of the proposed solution has been corroborated with numerical simulations. Moreover, no additional steps in fabrication processes are required with regard to the conventional SOI technology. 相似文献
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In this paper, we present a new technique for isolating the electrical behavior of an SOI MOSFET's from the self-heating effect using an AC conductance method. This method reconstructs an I-V curve by integrating high frequency output conductance data. The heating effect is eliminated when the frequency is much higher than the inverse of the thermal time constant of the SOI device. We present measurement results from SOI MOSFET's that demonstrate that heating can indeed be significant in SOI devices 相似文献
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Keunwoo Kim Ching-Te Chuang Kern Rim Jin Cai Wilfried E. Haensch 《International Journal of Electronics》2013,100(5):271-278
Compact physical models for SSOI MOSFETs are presented. The models consider specific features for strained-Si devices including SSOI such as mobility enhancement, band offsets, junction capacitance, and self-heating effects. All of the floating-body current components in conventional SOI structure, which are generation/recombination current, reverse-bias (band-to-band and trap-assisted) junction tunneling currents, gate-induced drain leakage current, gatebody oxide tunneling current, and impact ionization current are applied to the SSOI device, and their effects are discussed. The model validity is confirmed by fabricated 70?nm bulk-Si (control) and strained-Si devices. 相似文献
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SOI LDMOS晶体管的自加热效应 总被引:1,自引:0,他引:1
与常规体硅器件相比,SOI器件由于其独特的结构,常常会产生较严重的自加热效应,影响器件的可靠性.文中阐述SOI LDMOS功率晶体管中的自加热现象,研究了自加热效应产生的机理,在不同的结构和工艺参数下自加热效应的研究进展,以及减弱自加热效应的方法.研究证明采用新材料,结构可对同加热效应起到有效抑制作用提高了件的可靠性. 相似文献
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Sanjoy Deb N. Basanta Singh Debraj Das A.K. De 《International Journal of Electronics》2013,100(11):1465-1481
A generalised three-interface compact capacitive threshold voltage model for horizontal silicon-on-insulator/silicon-on-nothing (SOI/SON) MOSFET has been developed. The model includes different threshold voltage-modifying short-channel phenomena like fringing field, junction-induced 2D-effects, etc. Based on the threshold voltage model, an analytical current voltage model is formulated from the basic charge control analysis of MOSFET. In order to provide a better explanation to various observations and applicable to short-channel SOI and SON structures, the present current voltage model includes the effect of carrier velocity saturation and channel length modulation. Identical structures for both the devices, SOI and SON, are considered but for SON MOSFET, the buried oxide layer is replaced by air. The performance of the two devices are studied and compared in terms of threshold voltage roll-off, subthreshold slope, drain current and drain conductance. The SON MOSFET technology is found to offer devices with further scalability and enhanced performance in terms of threshold voltage roll-off, sub-threshold slope and greater current derivability, thereby providing scope for further miniaturisation of devices and much better performance improvement. 相似文献
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MOS transistors with effective channel lengths down to 0.2 μm have been fabricated in fully depleted, ultrathin (400 Å) silicon-on-insulator (SOI) films. These devices do not exhibit punchthrough, even for the smallest channel lengths, and have performance characteristics comparable to deep-submicrometer bulk transistors. The NMOS devices have a p+-polysilicon gate, and the PMOS devices have an n+-polysilicon gate, giving threshold voltages close to 1 V with very light channel doping. Because the series resistance associated with the source and drain regions can be very high in such thin SOI films, a titanium salicide process was used using a 0.25 μm oxide spacer. With this process, the sheet resistance of the silicided SOI layer is approximately 5 Ω/□. However, the devices still exhibit significant series resistance, which is likely due to contact resistance between the silicide and silicon source/drain regions 相似文献
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In this paper, an analytic current-voltage model for submicrometer fully-depleted (FD) silicon-on-insulator (SOI) MOSFET's is presented. This model takes into account the source/drain series resistances which can be especially high in thin film SOI devices. The effect of drain induced conductivity enhancement is also included, which is important for submicrometer channels. The model is verified by comparison to measured SOI I-V characteristics. Good agreement is obtained for SOI film thicknesses ranging from 40 to 220 nm and effective channel lengths down to 0.25 μm 相似文献