一种基于JTAG的CLB内建自测试方法

针对Virtex-4型FPGA中可编程逻辑块故障检测的需求,提出了一种基于JTAG的内建自测试方法,并基于DEV++平台自行开发了基于并口的专用边界扫描测试软件.该方法可以比较可靠的检测FPGA中存在故障的可编程逻辑块,并能比较高的分辨率实现故障的定位.与传统的单故障检测方法相比,提出的改进型测试方法可以检测和定位多个故障CLB,并可以对故障类型进行诊断.实验结果表明:提出的测试方法可以精确的检测和定位存在故障的多个CLB,对具有类似结构的SRAM型FPGA具有普遍适用性.     

存储器内建自测试的程序控制方法

文中提出了一种利用处理器的指令系统编写特定程序,通过程序运行来控制完成整个存储器内建自测试过程的方法.基于此方法的设计已经成功应用于一款处理器中,有效地提高了芯片的可测试性和应用系统的容错性.     

基于内建自测试电路的NAND Flash测试方法

随着NAND Flash在存储器市场中的占比与日俱增,对NAND Flash的测试需求也越来越大。针对NAND Flash存储器中存在的故障类型进行讨论,并对现有测试算法进行分析,为提高故障覆盖率以及降低测试时间,对现有的March-like测试算法做出改进,改进算法比March-like算法的故障覆盖率提高了16.7%,测试时间减少了30%。完成存储器内建自测试（MBIST）电路设计,设计了FPGA最小系统板并进行板级验证,结果验证了MBIST电路以及改进的测试算法的可行性。     

On-Chip SRAM内建自测试及其算法的研究

具体研究on-Chip SRAM的内建自测试及其算法.在引入嵌入式存储器内建自测试的基础上,详细分析on-Chip SRAM内建自测试的具体实现方法,反映出内建自测试对于简化测试程序和缩短测试时间,从而降低测试成本的重要性.详细描述在测试on-Chip SRAM时常用的算法,并具体分析非传统性测试算法——Hammer算法和Retention算法.     

一种基于存储器内建自测试的新型动态March算法设计

存储器作为片上系统(SoC)中最大和最重要的模块之一,它的稳定性和可靠性关乎着整个芯片能否正常工作。为了提高存储器的测试效率,该文提出一种新型动态March算法——Dynamic-RAWC。相比经典的March RAW算法,Dynamic-RAWC算法有着更良好的故障检测效果：动态故障覆盖率提高了31.3%。这个可观的效果得益于所提算法以经典的March RAW算法为基础进行优化,融入了Hammer, March C+算法的测试元素和一些新的测试元素。不同于普通March型算法的固定元素,所提算法支持用户自定义算法的执行顺序以适应不同的故障检测需求,能够动态地控制算法元素,在时间复杂度和故障覆盖率之间进行调整从而达到良好的平衡。     

嵌入式存储器内建自测试时间的优化

存储器测试是集成电路测试的重要部分。随着集成电路存储器件向着高集成度发展,存储器测试成本在集成电路总测试成本中所占比例急剧增高。通过减少存储器测试时间来减小存储器测试成本,是一种高效的降低芯片测试成本的方法。本文以一款单周期同步存储器为例,选取读写时序为对象,详细分析了存储器内建自测试方法,给出了一种通过优化存储器内建自测试逻辑时序来减小存储器测试时间的设计实现方法。     

层次化设计方法在存储器内建自测试上的应用

本文简单介绍存储器内建自测试设计技术原理,针对具体的RTL实例,对自顶向下设计方法和层次化设计方法进行了比较。实例结果表明：层次化的设计方法在大型芯片的存储器内建自测试设计中,可以加速设计,减少设计迭代时间,大幅提高工作效率。     

基于部分扫描的低功耗内建自测试

在分析全扫描内建自测试 (BIST)过高测试功耗原因的基础上 ,提出了一种选择部分寄存器成为扫描单元的部分扫描算法来实现低功耗 BIST。实验表明 ,提出的方法在保证测试覆盖率的条件下能同时降低 BIST的峰值功耗和平均功耗 ,降幅分别高达 46%和 69%。     

嵌入式存储器内建自测试的原理及实现

随着集成电路设计规模的不断增大 ,在芯片中特别是在系统芯片 SOC( system on a chip)中嵌入大量存储器的设计方法正变得越来越重要。文中详细分析了嵌入式存储器内建自测试的实现原理 ,并给出了存储器内建自测试的一种典型实现。     

A Built-In Self-Test structure for measuring gain and 1-dB compression point of Power Amplifier

This paper proposes a Built-In Self-Test (BIST) structure for measuring the gain and the 1-dB compression point of the Power Amplifier (PA) in transceiver ICs. In this structure, it is not necessary to use the external devices for mapping and DC measuring because of linearity of blocks, comparative performance in the linear region and the digital representation of the 1-dB compression point and gain value. The BIST Circuit is designed and simulated in 180 nm RF-CMOS process with Spectre-RF for a 900 MHz PA while it can achieve an acceptable accuracy which the input referred 1-dB compression point and gain value can be obtained with an error of about 0.2 dBm and 0.18 dB, respectively and the testing time is about 25 µs depends on resolution. Finally, in order to verify the proposed approach, we implemented practically a similar discrete circuit as proof-of-concept prototype that it obtained input referred 1-dB compression point value with an error of about 0.15 dBm.     

A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs

This paper investigates the viability of an ADC BIST scheme for implementing the histogram test technique. An original approach is developed to extract the ADC parameters from the histogram with a minimum area overhead. In particular, it is shown that the choice of a triangle-wave input signal combined with an appropriate time decomposition technique of the test procedure permits to drastically reduce the required on-chip hardware circuitry.     

Availability model for self test and repair in fault tolerant FPGA-based systems

Dynamically reconfigurable Field Programmable Gate Array （dr-FPGA） based electronic systems on board mission-critical systems are highly susceptible to radiation induced hazards that may lead to faults in the logic or in the configuration memory.The aim of our research is to characterize self-test and repair processes in Fault Tolerant （FT） dr-FPGA systems in the presence of environmental faults and explore their interrelationships.We develop a Continuous Time Markov Chain （CTMC）model that captures the high level fail-repair processes on a dr-FPGA with periodic online Built-In Self-Test （BIST） and scrubbing to detect and repair faults with minimum latency.Simulation results reveal that given an average fault interval of 36 s,an optimum self-test interval of 48.3 s drives the system to spend 13％ of its time in self-tests,remain in safe working states for 76％ of its time and face risky fault-prone states for only 7％ of its time.Further,we demonstrate that a well-tuned repair strategy boosts overall system availability,minimizes the occurrence of unsafe states,and accommodates a larger range of fault rates within which the system availability remains stable within 10％ of its maximum level.     

24位BOOTH乘法器核的一种有效BIST方法

针对24位BOOTH乘法器核的可测性问题，提出了一种有效的BIST(built-in self-test)设计方案。这种方案只需要对乘法器进行少量的改动，缺陷测试覆盖率可以达到95％左右。该方案还可以应用到其他嵌入式核的可测性设计中。     

内建自测试的测试生成方法研究

内建自测试（BIST）方法是目前可测试性设计（DFT）中应用前景最好的一种方法,其中测试生成是关系BIST性能好坏的一个重要方面。测试生成的目的在于生成尽可能少的测试向量并用以获得足够高的故障覆盖率,同时使得用于测试的硬件电路面积开销尽可能低、测试时间尽可能短。内建自测试的测试生成方法有多种,文中即对这些方法进行了简单介绍和对比研究,分析了各自的优缺点,并在此基础上探讨了BIST面临的主要问题及发展方向。     

Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs

The objective of this paper is to propose a method to test all the delay faults located in Look-Up-Tables (LUTs) of SRAM-based symmetrical FPGAs. This method is developed in a Manufacturing-Oriented Context (MOT). In the first part of the paper, the timing behavior of the LUTs and the physical defects inducing delay faults in the LUTs are analyzed. Then, the detection conditions to test such delay faults are established and requirements on test vectors are derived. Finally a test configuration scheme and its associated test sequence able to test exhaustively the delay faults in all LUTs of a symmetrical FPGA are proposed.A preliminary version of this work has been presented at the European Test Workshop 2003, in MaastrichtThis revised version was published in March 2005 with corrections to one of the last authors name and the cover date.