Shortest bayes credibility intervals for the lognormal failure model

The lognormal distribution with density function

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Temperature dependent current–voltage (I–V) characteristics of Au/n-Si (1 1 1) Schottky barrier diodes with PVA(Ni,Zn-doped) interfacial layer

Current–voltage (I–V) characteristics of Au/PVA/n-Si (1 1 1) Schottky barrier diodes (SBDs) have been investigated in the temperature range 80–400 K. Here, polyvinyl alcohol (PVA) has been used as interfacial layer between metal and semiconductor layers. The zero-bias barrier height (Φ_B0) and ideality factor (n) determined from the forward bias I–V characteristics were found strongly dependent on temperature. The forward bias semi-logarithmic I–V curves for different temperatures have an almost common cross-point at a certain bias voltage. The values of Φ_B0 increase with the increasing temperature whereas those of n decrease. Therefore, we have attempted to draw Φ_B0 vs. q/2kT plot in order to obtain evidence of a Gaussian distribution (GD) of the barrier heights (BHs). The mean value of BH and standard deviation (σ₀) were found to be 0.974 eV and 0.101 V from this plot, respectively. Thus, the slope and intercept of modified vs. q/kT plot give the values of and Richardson constant (A^?) as 0.966 eV and 118.75 A/cm²K², respectively, without using the temperature coefficient of the BH. This value of A^* 118.75 A/cm²K² is very close to the theoretical value of 120 A/cm²K² for n-type Si. Hence, it has been concluded that the temperature dependence of the forward I–V characteristics of Au/PVA/n-Si (1 1 1) SBDs can be successfully explained on the basis of the Thermionic Emission (TE) theory with a GD of the BHs at Au/n-Si interface.     

Analyzing the error of an approximate method for computing performance-related reliability

An approximate method for computing performance-related reliability of large-scale gracefully degrading systems was developed. Examples show that the error of this method decreases with the increase of the number of units composing the system, N. However, a theoretical analysis is necessary to reveal the insight of this error reduction. In this paper, the error of the approximate method is analyzed. The result shows that, in both cases, i.e. reconfiguration coverage C = 1 and C < 1, the truncation error of the resulting performance-related reliability is of the order , showing a significant error decrease of the new method with the increase of N.     

An optimal open-loop multimode fiber gyroscope for rate-grade performance applications

We report the realization of a new version of a fiber optic gyroscope (FOG), using low-cost multimode fiber components. This is achieved by an optimal choice of the components such as fiber, coupler, light source and photodetector. The aim behind this work is to demonstrate the versatility of the low-cost multimode FOG for rate-grade performance applications. Both analog signal processing and open-loop operation are used in the proposed FOG experiment. The obtained sensitivity is ∼7°/h and the angle random walk is about 0.087°/. The influence of the coupler technology on the performances is investigated.     

A CMOS image sensor with light-controlled oscillating pixels for an investigative optobionic retinal prosthesis system

This paper presents a high-dynamic range CMOS image sensor architecture incorporating light-controlled oscillating pixels which can act as front-end for an investigative optobionic retinal prosthesis research effort. Each pixel acts as an independent oscillator, whose frequency is proportional to the local light intensity. A 9×9 pixel array has been fabricated in the AMS CMOS opto process. Each pixel's area amounts to , each pixel photodiode area is while the array occupies . Measured results show that the sensor can achieve a linear optical dynamic range of 80 dB (from 0.24 Hz to 2.2 kHz). Its linear electrical dynamic range exceeds 134 dB (from 100 mHz to 502 kHz). The nominal power dissipation is about 50 nW per pixel.     

Low power impedance measurement integrated circuit for sensor applications

In this paper an integrated circuit for the measurement of the real and imaginary part of an impedance is presented. The circuit is intended for its use in a wireless integrated system. A mixed analog/digital approach has been adopted in order to minimize power and area requirements, as requested by the application. The four electrode configuration is used for impedance measurement using two excitation current sources and a buffer instead of an instrumentation amplifier, therefore reducing the circuit complexity. The digital block controls the working frequency and can compensate the phase error introduced by the analog filters, thereby reducing the total error in the measurement. The integrated circuit has been designed in a CMOS process and it works with 3.3 V with a power consumption of . Experimental results to verify its functionality are presented.     

A novel ADPLL design using successive approximation frequency control

This paper presents a hardware implementation of a fully synthesizable, technology-independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter. Frequency control is done by using a robust regulation algorithm to allow a defined lock-in time of at most eight reference cycles. ASICs in CMOS AMS and UMC have been manufactured and tested. Measurements show competitive results to state-of-the-art mixed-signal implementations.     

Design and design methods for unified multiplier and inverter and its application for HECC

This paper describes two novel architectures for a unified multiplier and inverter (UMI) in GF(2^m): the UMI merges multiplier and inverter into one unified data-path. As such, the area of the data-path is reduced. We present two options for hyperelliptic curve cryptography (HECC) using UMIs: an FPGA-based high-performance implementation (Type-I) and an ASIC-based lightweight implementation (Type-II). The use of a UMI combined with affine coordinates brings a smaller data-path, smaller memory and faster scalar multiplication.Both implementations use curves defined by h(x)=x and f(x)=x⁵+f₃x³+x²+f₀. The high throughput version uses 2316 slices and 2016 bits of block RAM on a Xilinx Virtex-II FPGA, and finishes one scalar multiplication in . The lightweight version uses only 14.5 kGates, and one scalar multiplication takes 450 ms.     

A high precision low dropout regulator with nested feedback loops

A high precision low dropout regulator (LDO) with nested feedback loops is proposed in this paper. By nesting a zero-tracking compensation loop inside of the negative feedback loop comprising an error amplifier, the independence of off-chip capacitor and effective series resistance (ESR) is ensured for different load currents and operating voltages. This circuit is designed and fabricated using a standard CMOS process. The die area is a . The measurement results show that the total error of the output voltage caused by line and load variations is less than ±3% in low quiescent current (Iddq) or low voltage scenarios. Besides, the smallest dropout of the LDO, 0.11 V, while the output current is 165 mA, the output load is and 20 in parallel.     

Study of Cu diffusion in an Al–1 wt.%Si–0.5 wt.%Cu bond pad with an Al–1 wt.%Si bond wire attached using scanning electron microscopy

A study with scanning electron microscopy (SEM) and scanning transmission electron microscopy (STEM) of the Al–1 wt.%Si–0.5 wt.%Cu bond pad metallisation with Al–1 wt.%Si wires bonded to it revealed Cu diffusion from the bond pad into the Al wire after an annealing process. Investigation at different annealing times showed a Cu depletion zone which indicates that the radius R is consistent with a behaviour. The diffusion velocity, as determined experimentally, is close to the velocity of grain boundary diffusion. This observation has important consequences with respect to electromigration testing of Al(Si)Cu metallisations bonded with Al wires. The electromigration (EM) process can be influenced by a bad placement of the Al bond wire with regard to the test lines. If bonded too close to the test line, Cu diffusion out of the test line is possible during annealing, thereby changing the microstructure locally and thus the EM process.     

Properties of wurtzite GaN MESFETs studied by two-dimensional full band Monte Carlo approach

The properties of a GaN Metal-Semiconductor Field Effect Transistor were studied based on two-dimensional full band Monte Carlo simulations. The dependences of the distributions of the electric potential, electron concentration, electric field, drift velocity, and average electron energy on the gate-source voltage (V_GS) and drain-source voltage (V_DS) were obtained, then the characteristics of the drain current (I_DS) versus the drain-source voltage (V_DS) and the transconductance (G_m) versus V_GS characteristics were determined. At and I_DS is 5.03 A/cm, which is higher value. The G_m−V_GS curve shows bell shaped and the maximum G_m is 112 ms/mm at and The current gain cutoff frequency (f_T) is 98 GHz at and      

Hot-carrier stress effects on the amplitude of Random Telegraph Signals in small area Si p-MOSFETS

This paper studies the effect of avalanche hot-carrier (HC) stress on the amplitude of pre-existing Random Telegraph Signals (RTSs) in small area Si p-MOSFETs. It is shown that the RTS amplitude of a particular oxide trap increases after HC stress, both in linear operation and in saturation. From this, it is concluded that the effect of such a trap on the carrier transport in a small area MOSFET is also determined by the charges present at the interface and in the oxide. The impact of the observations on the RTS based modeling of flicker noise in MOSFETs will be briefly addressed.     

Ionic outgassing from photoacid generators upon irradiation at 13.5 nm

Photoresist outgassing is considered a possible source of contamination of optics in extreme ultraviolet (EUV) lithography at 13.5 nm. We measured the relative proportions of ionic outgassing from 18 commercially available photoacid generators (PAG), which is a key component of chemically amplified photoresists, upon irradiation at 13.5 nm. These PAG include 17 triarylsulfonium or diaryliodonium salts, which contain or as the anion, and one PAG of molecular type. The overall outgassed ions in the range 10-200 u were counted in relative proportions. Outgassing of F⁺ is found to be dominant, and for most PAG the extent of F⁺ outgassing shows a satisfactory correlation with the ratio of F atomic photoabsorption to the overall PAG photoabsorption. Outgassed ions F⁺, CF⁺, and from PAG containing the anion and additional such as , and from those containing are identified. Triphenylsulfonium perfluoro-1-butanesulfonate is one PAG to emit the most abundant F⁺ and total ionic fragments, and a PAG of molecular type (N-hydroxy-5-norbornene-2,3-dicarboximide perfluoro-1-butanesulfonate) also emits abundantly both hydrocarbon ions and F⁺. Ionic outgassing of PAG cations includes (C₆H₅)₂S⁺ from R(C₆H₅)₂S⁺ salts and I⁺ from diaryliodonium salts. For PAG containing t-C₄H₉, significantly less F⁺ outgassing is observed; additional outgassing pathways are proposed. The pressure rise caused by PAG shows no dependence on the anion identity, but is correlated with cation photoabsorption, and ascribed to neutral aryl outgassing. Other minor outgassing species include from sulfonates; and ‘photostable’ PAH cations are identified for the first time and provide evidence of concurrent outgassing from, and polymerization of, PAG upon irradiation at 13.5 nm.     

A 1-V RF-CMOS LNA design utilizing the technique of capacitive feedback matching network

In this paper, a CMOS low-noise amplifier (LNA) with a new input matching topology has been proposed, analyzed and measured. The input matching network is designed through the technique of capacitive feedback matching network. The proposed LNA which is implemented in a technology is operated at the frequency of 12.8 GHz. It has a gain S21 of 13.2 dB, a noise figure (NF) of 4.57 dB and an NF_min of 4.46 dB. The reverse isolation S12 of the LNA can achieve and the input and output return losses are better than . The input 1-dB compression point is and IIP3 is . This LNA drains 10 mA from the supply voltage of 1 V.     

Electrical and structural characterization of PLD grown CeO2–HfO2 laminated high-k gate dielectrics

The electrical and physical properties of CeO₂–HfO₂ nanolaminates deposited by pulsed laser deposition (PLD) are investigated. The properties of the nanolaminates are compared with binary CeO₂ and HfO₂ thin films. Layers were deposited using CeO₂ and HfO₂ targets at substrate temperatures between 220 and 620 °C in 10 Pa Ar+H₂ or O₂. In situ post deposition anneal (PDA) was achieved by controlled cooling down to room temperature with . Nanolaminates starting with CeO₂ show lower EOT and leakage compared to layers starting with HfO₂. TEM and XRD analyses showed thickness-dependent crystallinity of the layers, varying from amorphous to highly oriented polycrystalline phase.C–V and I–V measurements were done on the capacitors. Lowest fixed-charge density was found for the nanolaminates deposited at 520 °C. The k values of the nanolaminates extracted by the EOT-physical thickness plots were found to be 141, 48 and 22, for deposition temperatures 420, 520 and 620 °C, respectively. Higher k value for lower deposition temperatures is explained by the thickness dependent morphology of the layers. An with was found for binary HfO₂ layer with 4 nm physical thickness. Lowest leakage current density was for a 4 nm laminate deposited at 420 °C and with a cooling rate of 2 °C/min during PDA.     

A novel nonvolatile memory based on self-organized quantum dots

A novel type of memory based on self-organized quantum dots (QDs) is presented, which merges the advantages of the most important semiconductor memories, the dynamic random access memory (DRAM) and the Flash. A nonvolatile memory with fast access times and good endurance (>10¹⁵ write/erase cycles) as an ultimate solution seems possible. A storage time of 1.6 s at 300 K in InAs/GaAs QDs with an additional Al_0.9Ga_0.1As barrier is demonstrated and a retention time of 10⁶ years is predicted for GaSb QDs in an AlAs matrix. A minimum write time of 6 ns is obtained for InAs/GaAs QDs. This value is already in the order of the access time of a DRAM cell and at the moment limited by the RC low pass of the device. An erase time of milliseconds is shown in first measurements on GaSb/GaAs QDs at . Faster write/erase times below even at room temperature are expected for improved device structures.     

Structure analysis of the system Hafnium/Silicon by means of X-ray photoelectron spectroscopy and X-ray photoelectron diffraction (XPD)

Due to the ongoing miniaturization of semiconductor devices new gate dielectrics are required for future applications. In this work we investigated hafnium silicide as a pre-system for hafnium oxide, one of the most promising candidates. One of the major problems of HfO₂-films on silicon is the formation of hafnium silicide at the HfO₂/Si interface. Therefore, ultrathin films of the system HfSi on with a systematic varied thickness from 3 to 30 Å were prepared. Measurements were conducted by means of X-ray photoelectron spectroscopy and low energy electron diffraction (LEED). Also full 2π X-ray photoelectron diffraction (XPD) patterns with high spectral resolution were recorded. Against other reports related to thicker films, several heating cycles showed no phase transitions of the ultrathin films. However, above temperatures of an island formation is strongly indicated. The experimental XPD patterns are compared to simulated patterns of model structures. For the first time we present a modification of the C49 structure a possible structure for ultrathin HfSi₂-films on bulk Si. As an outlook possibilities for preparing the system are introduced.     

Barrier characteristics of gold Schottky contacts on moderately doped n-InP based on temperature dependent I-V and C-V measurements

The temperature dependences of current-voltage (I-V) and capacitance-voltage (C-V) characteristics of the gold Schottky contacts on moderately doped n-InP (Au/MD n-InP) Schottky barrier diodes (SBDs) have been systematically investigated in the temperature range of 60-300 K. The main diode parameters, ideality factor (n) and zero-bias barrier height (apparent barrier height) were found to be strongly temperature dependent and while the decreases, the n and the increase with decreasing temperature. According to Thermionic Emission (TE) theory, the slope of the conventional Richardson plot [In(J₀/T²) vs. 1000/T] should give the barrier height. However, the experimental data obtained do not correlate well with a straight line below 160 K. This behaviour has been interpreted on the basis of standard TE theory and the assumption of a Gaussian distribution of the barrier heights due to barrier inhomogeneities that persist at the metal-semiconductor interface. The linearity of the apparent barrier height vs. 1/(2kT) plot that yields a mean barrier height of 0.526 eV and a standard deviation (σ_s0) of 0.06 eV, was interpreted as an evidence to apply the Gaussian distribution of the barrier height. Furthermore, modified Richardson plot [ vs. 1/T] has a good linearity over the investigated temperature range and gives the and the Richardson constant (A^∗) values as 0.532 eV and 15.90 AK⁻²cm⁻², respectively. The mean barrier heights obtained from both plots are appropriate with each other and the value of A^∗ obtained from the modified Richardson plot is close to the theoretical value of 9.4 AK⁻²cm⁻² for n-InP. From the C-V characteristics, measured at 1 MHz, the capacitance was determined to increase with increasing temperature. C-V measurements have resulted in higher barrier heights than those obtained from I-V measurements. The discrepancy between Schottky barrier heights(SBHs) obtained from I-V and C-V measurements was also interpreted. As a result, it can be concluded that the temperature dependent characteristic parameters for Au/MD n-InP SBDs can be successfully explained on the basis of TE mechanism with Gaussian distribution of the barrier heights.