Improved architecture for low-distortion δσ ADC's

The low-distortion modulator is an effective ΔΣ ADC architecture for high-linearity and low-dissipation applications. However, it has several practical drawbacks. An improved low-distortion modulator topology that avoids these disadvantages is suggested.     

Double-sampled ΔΣ modulator with relaxed feedback timing

A double-sampled delta-sigma (ΔΣ) modulator topology is proposed that can relax the critical timing constraints in the modulator feedback path. The speed requirements of the quantiser and dynamic element matching logic are thus greatly reduced. To verify the effectiveness of the proposed topology, a second-order double-sampled DS modulator is designed and simulated.     

Comparator-less digital implementation of AC-coupled ΣΔ A/D converters

A simple and successful design for a sigma-delta (ΣΔ) modulator with only digital active components is presented. Low frequency compensation of the input threshold variations of the digital gate used as a comparator achieves good spurious-free dynamic range. The only drawback is the addition of a low cutoff frequency, which results in an AC-coupled analogue-to-digital converter.     

Resonation-based cascade ΣΔ modulator for broadband low-voltage A/D conversion

A novel cascade SigmaDelta modulator architecture is presented that employs inter-stage resonation to increase its effective resolution compared to traditional cascades while presenting very relaxed output swing requirements and, subsequently, high robustness to nonlinearities of the amplifiers. In addition, the use of loop filters based on forward-Euler integrators, instead of backward-Euler integrators as proposed in earlier approaches, simplifies the switched-capacitor implementation and makes the proposed architecture very suited to wideband A/D conversion.     

A Wideband ΔΣ Digital-RF Modulator for High Data Rate Transmitters

A wideband software-defined digital-RF modulator targeting Gb/s data rates is presented. The modulator consists of a 2.625-GS/s digital DeltaSigma modulator, a 5.25-GHz direct digital-RF converter, and a fourth-order auto-tuned passive LC RF bandpass filter. The architecture removes high dynamic range analog circuits from the baseband signal path, replacing them with high-speed digital circuits to take advantage of digital CMOS scaling. The integration of the digital-RF converter with an RF bandpass reconstruction filter eliminates spurious signals and noise associated with direct digital-RF conversion. An efficient passgate adder circuit lowers the power consumption of the high-speed digital processing and a quadrature digital-IF approach is employed to reduce LO feedthrough and image spurs. The digital-RF modulator is software programmable to support variable bandwidths, adaptive modulation schemes, and multi-channel operation within a frequency band. A prototype IC built in 0.13-mum CMOS demonstrates a data rate of 1.2 Gb/s using OFDM modulation in a bandwidth of 200 MHz centered at 5.25 GHz. In-band LO and image spurs are less than -59 dBc without requiring calibration. The modulator consumes 187 mW and occupies a die area of 0.72 mm².     

A 12-bit 3.125 MHz Bandwidth 0–3 MASH Delta-Sigma Modulator

We demonstrate a 12-bit 0–3 MASH delta-sigma modulator with a 3.125 MHz bandwidth in a 0.18 $muhbox{m}$ CMOS technology. The modulator has an oversampling ratio of 8 (clock frequency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 $~$dB peak SNR) and consumes 24 mW from a 1.8 V supply. For comparison purposes, the modulator can be re-configured as a single-loop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is obtained with 22 mW power consumption. The energy required per conversion step for the 0–3 MASH architecture (0.95 pJ/step) is less than half of that required by the feedback topology (2.57 pJ/step).      

5.2 mW 61 dB SNDR 15 MHz Bandwidth CT ΔΣ Modulator Using Single Operational Amplifier and Single Feedback DAC

We propose an architecture that reduces the power consumption and active area of such a modulator through a reduction in the number of active components and a simplification of the topology. The proposed architecture reduces the power consumption and active area by reducing the number of active components and simplifying the modulator topology. A novel second‐order loop filter that uses a single operational amplifier resonator reduces the number of active elements and enhances the controllability of the transfer function. A trapezoidal‐shape half‐delayed return‐to‐zero feedback DAC eliminates the loop‐delay compensation circuitry and improves pulse‐delay sensitivity. These simple features of the modulator allow higher frequency operation and more design flexibility. Implemented in a 130 nm CMOS technology, the prototype modulator occupies an active area of 0.098 mm² and consumes 5.23 mW power from a 1.2 V supply. It achieves a dynamic range of 62 dB and a peak SNDR of 60.95 dB over a 15 MHz signal bandwidth with a sampling frequency of 780 MHz. The figure‐of‐merit of the modulator is 191 fJ/conversion‐step.     

The multivariate α-μ distribution

An infinite series formulation for the multivariate α-μ joint probability density function with arbitrary correlation matrix and non-identically distributed variates is derived. The expression is exact and general and includes all of the results previously published in the literature concerning the distributions comprised by the α-μ distribution. The general expression is then particularized to an indeed very simple, approximate closed-form solution. In addition, a multivariate joint cumulative distribution function is obtained, again in simple, closed-form manner. As an application example, the exact and approximate performances of the selection combining scheme given in terms of the outage probability is shown. Approximate and exact results are very close to each other for small as well as medium values of correlation.     

0.5-25 GHz inductorless single-ended resistive mixer in 0.13 μm CMOS

A wideband inductorless resistive down-conversion mixer in 0.13 μm CMOS technology is presented. The mixer provides a conversion loss of 9?11.7 dB over a frequency range of 0.5?25 GHz at LO power of 6 dBm. The circuit exhibits an input-referred 1 dB compression point and IIP3 of 4.7 and 11.5 dBm, respectively. The mixer consumes only 0.2 mA from 1.5 V for biasing. The isolation between the ports is higher than 10 dB for the whole frequency range. The circuit is realised without inductors, thus offering very wide bandwidth. The chip size including the pads is 0.23 mm², and the circuit active area is only 0.014 mm².     

Switched-Current bandpass Sigma–Delta modulators for AM digital radio receivers

This paper discusses the use of switched-current (SI) circuits to design Band-Pass ΣΔ Modulators (BP-ΣΔMs) suitable for AM digital radio receivers. First of all, the paper briefly outlines the concept and principles of BP-ΣΔMs, and introduces two modulator architectures which are obtained by applying a lowpass-to-bandpass transformation (i.e. z⁻¹→−z⁻²) to a first-order and a second-order Low-Pass ΣΔ Modulator (LP-ΣΔM), respectively. The resulting BP-ΣΔMs, respectively of second-order and of fourth-order, are then used as case studies for SI circuit implementation. Systematic analysis of the errors associated to SI circuits is carried out and models are presented to evaluate their incidence on the performance of BP-ΣΔMs; the significance of the different errors is illustrated via the two selected case studies. Fully-differential regulated-folded cascode SI memory cells are chosen to attenuate these errors. Based on the proposed error models, optimization is carried out to fulfill AM radio requirements in practical modulator implementations. Two IC prototypes have been fabricated in a CMOS 0.8 μm technology, and measured, to validate the presented design methodology. One of these prototypes uses the fourth-order architecture to digitize AM signals, and features 10.5-bit resolution with 60 mW power consumption from a 5 V supply voltage. The other uses the second-order architecture and features 8-bit with 42 mW in the commercial AM band, from 540 to 1600 kHz. Experimental results show correct noise-shaping for sampling frequencies up to 16 MHz, which means a significant operation frequency enhancement as compared to previously reported SI ΣΔ Modulators.     

CMOS fully-differential bandpass ΣΔ modulator usingswitched-current circuits

The authors present a fourth-order bandpass ΣΔ switched-current modulator IC in 0.8 μm CMOS single-poly technology. It is the first reported integrated circuit realisation of a bandpass ΣΔ modulator using switched-current circuits. Its architecture is obtained by applying a lowpass to bandpass transformation (z¹→-z²) to a second-order lowpass modulator. It has been realised using fully-differential circuitry with common-mode feedback. Measurements show 8 bit dynamic range up to 5 MHz clock frequency     

Signal adaptive control architecture for ΔΣ modulatordesign

A signal adaptive control architecture for a second-order ΔΣ modulator design is presented. This architecture effectively reduces the power dissipation and the distortion of the first stage in the modulator. The function of this architecture is to switch off the DAC feedback signal to the first stage during some iterations, and to compensate the signal at the second stage, in an adaptive manner     

Noise-shaped integrating quantisers in ΔΣ modulators

A new integrating analogue-to-digital converter (ADC) is proposed. With a small modification to the discharging phase of the traditional single/dual slope converter, error correction may be achieved. If the corrected ADC is embedded in a delta-sigma (DeltaSigma) converter, first-order quantisation noise shaping is achieved. This enhances the noise shaping of the delta-sigma modulator. Simulation results are provided to verify the effectiveness of this structure.     

Σ-Δ插值型A/D转换器的结构优化设计

该文提出了一种新的通用高阶稳定的∑-△插值型A/D转换器的优化设计算法.该算法采用状态空间下通用的插值型结构,研究了设计原理和设计的详细过程,给出了传输函数变换和稳定条件,实现了零点优化和巴特沃思极点的噪声传递函数.在结构系数的实现中,采用能量增量最小的优化算法,使A/D转换器具有更佳的稳定性能.最后,通过例子验证了该方法的有效性.     

A 1.8-V MOSFET-only ΣΔ modulator using substrate biaseddepletion-mode MOS capacitors in series compensation

A low-voltage high-linearity MOSFET-only ΣΔ modulator for speech band applications is presented. The modulator uses substrate biased MOSFETs in the depletion region as capacitors, linearized by a series compensation technique. A second-order fully differential single-loop architecture has been realized in a conventional 0.25-μm digital n-well CMOS process without extra layers for capacitors. An SNDR of 72 dB and an SNR of 77 dB is obtained with 8-kHz signal bandwidth at an oversampling ratio of 64. The circuit consumes about 1 mW from a single 1.8-V power supply and occupies a core area of 0.08 mm²     

Dynamic range extension technique for high-order ΣΔADCs by digital level control

A new architecture is presented for a high-order multi-bit ΣΔ ADC which does not require a precision multi-bit DAC in the feedback loop. Local digital level control is employed to extend integrator output dynamic range. A prototype fourth-order modulator is simulated with circuit non-idealities, showing an SNR of ~110 dB     

Mid-infrared GaSb-based EP-VCSELl emitting at 2.63 μm

Electrically-pumped GaSb-based vertical-cavity surface-emitting lasers emitting up to 2.63 μm at room temperature are reported. The whole structure was grown monolithically in one run by solid-source molecular beam epitaxy. This heterostructure is composed of two n-doped AlAsSb/GaSb DBRs, a type-I GaInAsSb/AlGaAsSb multiquantum- well active region and an InAsSb/GaSb tunnel junction. A quasi-CW (1 μs, 5 %) operation was obtained at room temperature for 35 μm-diameter devices with threshold current of 85 mA.     

Development of the Area-Reducing Active “Coil-Enhancement” Principle, Practiced Onto an ADSL–POTS Splitter

This paper describes the theory behind the “coil-enhancement” principle: The impedance of an inductor is made controllable as a function of the frequency by means of a transconductance function ${g}_{m} ({s})$ that is located in the feedback loop. In order to show the potential of the coil-enhancement circuit, the effect of several basic transconductance functions onto the synthesized impedance is presented. The specific case of ${g}_{m} ({s}) sim {s}^{-1}$ produces the coil-enhancement situation and is discussed in detail. One drawback of the coil-enhancement circuit is found in the series resistance of a second inductor, also positioned in the feedback loop. The influence of this series resistance onto the synthesized impedance is addressed and a work-around is presented. A newly developed active “plain old telephone service” (POTS) splitter, based upon the coil-enhancement principle, is derived from a fully passive POTS splitter in which two large inductors are merged together into one active inductor. The active POTS splitter is fully tested and is found compliant with the standard “TS 101 952-1-1 V1.2.1 (option A)” of the European Telecommunications Standards Institute. The area reduction that comes together with the passive-to-active conversion is 40%.      

70-MHz IF 10-MHz bandwidth bandpass \Upsigma\Updelta modulator for WCDMA applications

A MASH bandpass $\Upsigma\Updelta$ modulator for wide-band code division multiple access (WCDMA) applications is presented. The signal bandwidth of the proposed modulator is 10?MHz centered around an intermediate frequency (IF) of 70.5?MHz. Two two-path second-order bandpass $\Upsigma\Updelta$ modulators make the MASH architecture, which realizes a noise transfer function with four couples of complex conjugate zeros. The proposed circuit, fabricated with a 0.18???m CMOS technology, uses a sampling frequency of 180?MHz to obtain a resolution of about 12?bits in the 10?MHz bandwidth around the IF. The measured modulator power consumption is 95?mW with a supply voltage of 1.8?V. The achieved figure-of-merit (FoM _BP ) is 0.37?pJ/conversion-level.     

A two-path bandpass ΣΔ modulator for digital IFextraction at 20 MHz

Oversampled bandpass A/D converters based on sigma-delta (ΣΔ) modulation can be used to robustly digitize the types of narrowband intermediate frequency (IF) signals that arise in radios and cellular systems. This paper proposes a two-path architecture for a fourth-order, bandpass modulator that is more tolerant of analog circuit limitations at high sampling speeds than conventional implementations based on the use of switched-capacitor biquadratic filters. An experimental prototype employing the two-path topology has been integrated in a 0.6-μm, single-poly, triple-metal CMOS technology with capacitors synthesized from a stacked metal structure. Two interleaved paths clocked at 40 MHz digitize a 200-kHz bandwidth signal centered at 20 MHz with 75 dB of dynamic range while suppressing the undesired mirror image signal by 42 dB. At low input signal levels, the mixing of spurious tones at DC and f_s/2 with the input appears to degrade the performance of the modulator; out-of-band sinusoidal dither is shown to be an effective means of avoiding this degradation. The experimental modulator dissipates 72 mW from a 3.3 V supply