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1.
Ion projection lithography is developed to generate structures with minimum feature sizes in the 100-nm range with a high pixel transfer rate. The high depth of focus (DOF) resulting from the telecentric beam path concept is also noteworthy. A silicon wafer exhibiting 200-μm-deep cavities, which are fabricated by anisotropic etching, is patterned with a grating of 0.6 μm periodicity running with identical spacings from the bottom to the top. SiO2 serves as an inorganic ion sensitive resist. Exposed to 73 keV helium ions, SiO2 shows an enhanced etching rate in hydrofluoric acid, the structure developing agent. The patterning techniques considered are promising for the fabrication of two-dimensional reflecting mirrors or sensoric elements distributed on spherical surfaces  相似文献   

2.
SiO2 and Si3N4, are usually used to mask the selected portions during etching of silicon in anisotropic etchants like KOH but polymers are expected to be very good alternative to SiO2 and Si3N4 as masking materials for MEMS applications. An adherent spin coated PMMA layer is reported to work as a mask material. It is a low temperature process, cheaper and films can be easily deposited and removed. One of the problems in its use is its adhesion to the substrate. Our previous experience in the field made us feel that sputtered PMMA will act as better mask because of its better adhesion to silicon. In the present article, a comparative study of spin coated PMMA with sputtered PMMA as an etch mask for silicon micromachining is reported. Structural and adhesive characteristics of the films are determined and compared with those available in the literature. These films deposited on silicon wafer were exposed to anisotropic etchant, KOH, to estimate the masking behavior. The maximum masking time of 32 min in 20 wt.% KOH at 80 °C was obtained for spin coated PMMA samples, which were prebaked at 90 °C. Masking time of sputter deposited PMMA films was found to be 300 min under similar conditions such as 20 wt.% KOH at 80 °C. This masking time is sufficient for fabrication of various MEMS structures, thus indicating candidature of sputtered PMMA as masking material. Various properties of the films are discussed and compared with the ones obtained through literature.  相似文献   

3.
The selective removal of the substrate from under devices can help improve Q-factors, reduce losses and parasitics and can be applied to microwave components (transmission lines, spiral inductors, and capacitors) critical to high-frequency communications systems. A novel molding process has been developed to produce cavities in ceramic substrates over which gold transmission lines can be suspended. The "additive" method of fabricating cavities in ceramics was primarily based on the production of a substrate with preexisting cavities, as opposed to generation of cavities by the removal or the "subtraction" of material. The preexisting cavities were generated using a transfer mold technique based on photolithography, anisotropic silicon etching and nickel electroplating. The approach was demonstrated successfully using a commercial glass ceramic material (DuPont 951 Green Tape) to yield 100-/spl mu/m-deep cavities that showed shape retention and dimensional stability.  相似文献   

4.
Dry release for surface micromachining with HF vapor-phase etching   总被引:1,自引:0,他引:1  
A new method for dry etching of silicon dioxide for surface micromachining is presented to obtain very compliant polysilicon microstructures with negligible stiction problem and to greatly simplify the overall releasing procedure as well. By etching the sacrificial silicon dioxide with hydrofluoric acid (HF) vapor instead of conventional aqueous HF solution, the need for subsequent rinsing and an elaborate drying procedure is eliminated. Condensation of water on the etch surface is first identified as the cause that prevented the success of HF vapor release in the past. Use of an anhydrous HF/CH3OH mixture under low pressure solves the problem of water condensation and enables us to take advantage of vapor-phase etching (VPE) for surface micromachining. The mechanism of oxide etching with the HF/CH3OH mixture is explained, and the developed VPE system is described and characterized. Polysilicon cantilevers up to 1200 μm in length are successfully released with this HF VPE technique. The beams tested are 2 μm thick with a 2-μm gap from the substrate, and no antistiction dimples are used. The fabricated structures are observed using both scanning electron microscopy (SEM) and an optical profilometer. The reported VPE technique provides a robust releasing method for polysilicon microstructures and is compatible with integrated circuit (IC) fabrication, even including cluster processors  相似文献   

5.
This paper presents micromachined solenoid inductors that are fabricated in a standard CMOS silicon substrate (with a resistivity of 1-8 Omega . cm). The solenoid is concavely embedded in a silicon cavity with the silicon wafer surface remaining a plane, and mechanically suspended to form an air gap from the bottom of the silicon cavity. In addition to facilitating flip-chip packaging, this so-called "concave-suspending" technique effectively depresses the substrate effects including eddy current and capacitive coupling between the coil and the substrate, therefore contributing to both high Q -factor and high resonant frequency of the inductors for high-performance radio-frequency (RF)/microwave integrated circuit applications. Various inductors with different solenoid layouts, e.g., several shapes of curved solenoids, have been successfully fabricated by using a post-CMOS microelectromechanical systems process that employs copper electroplating, tetra-methyl-ammonium hydroxide (TMAH) + iso- propanol etching and compensation control for convex-corner undercutting, photoresist spray coating, XeF2 gaseous etching, and other steps. A lumped circuit model that accounts for inter- turn fringing capacitance, capacitance between the coil and the substrate, substrate ohmic loss and substrate capacitance, etc., is derived for the solenoid inductors. The accuracy of the model is confirmed by the testing results and can be used for optimal design of the inductors. By S-parameter testing, various types of inductors with different solenoid layouts have been evaluated. The solenoid inductors generally exhibit improved RF performance in Q-factor and self-resonance frequency compared to their conventional counterparts.  相似文献   

6.
Filling trenches in silicon using phosphosilicate glass (PSG) provides many possibilities for novel device structures for sensors and actuators. This paper describes a plasma planarization technique that provides fully planarized PSG filled silicon trenches for sensor applications. The technique consists of planarizing the substrate using two photoresist layers and plasma etching-back. The lower resist layer is the AZ5214 image reversal resist, which is patterned and then thermally cured. The upper resist layer is a global HPR204 coating. The plasma etching-back is carried out using CHF3/C2F 6 gas mixture with an O2 addition. It is shown that by using the image reversal photoresist approach, fully planarized surface coating can be obtained without resorting to an additional mask. By adding 25 sccm (14%) O2 into the 137 sccm CHF3+18 sccm C2F6 gas mixture, the etch rates for the photoresist and PSG can be matched. Process optimization for the two layer resist coating and plasma etching is discussed  相似文献   

7.
This paper presents the development of micromachined thin-film silicon microbolometers which can be used for detection of soft X-ray, UV, visible and infrared radiation. The detector structure is a 1 μm thick polysilicon/Si3N4 membrane suspended over a cavity. This structure has been obtained by anisotropic etching of silicon with a previously deposited polysilicon/Si3N4 sandwich. Alternatively, porous silicon has been used as the sacrificial layer. Devices have been characterized. Good values of the voltage responsivity and detectivity have been obtained.  相似文献   

8.
A technology for surface micromachining of free-standing metal microstructures using metal electrodeposition on a sacrificial photoresist layer has been applied to a condenser microphone. Electroplating technology has been used to implement a suspended and perforated 15-μm-thick microstructure in copper, which serves as backplate electrode in the condenser microphone. The 1.8×1.8 mm 2 large microphone diaphragm is in monocrystalline silicon and is fabricated with anisotropic etching of the substrate wafer. The realized prototypes have a measured sensitivity of 1.4 mV/Pa using a bias voltage of 28 V. The bandwidth is limited by an anti-resonance at 14 kHz which is due to the semi-rigid backplate. The resonance behavior of the backplate structure has been analyzed with finite element modeling with results in good agreement with measured data  相似文献   

9.
Typical release for structures in microelectromechanical systems (MEMS) devices requires the use of sacrificial layers and wet etchants. As an alternative, bulk Si can be utilized for nonsilicon MEMS or structures as the sacrificial material when exposed to vapor-phase XeF2 . This paper presents the results of using relatively high pressures (> 3.0 torr) for the purpose of MEMS processing, while characterizing the physical etching mechanism and its effects on the working Si substrate in relation to the allowed processing time. The observed etch rates for high-pressure release varied from 1.6 to 1.9 mum/min for applied pressures of 4.5-5.5 torr. The resulting roughness is shown to be primarily dependent on time, where the maximum average roughness is approximately 1.4 mum after 3000 s at 5.5 torr. Slightly anisotropic results are produced by the increased pressures, showing a 0.7 : 1.0 (vertical : lateral) etch rate, as well as some detrimental effects to the released structures. Furthermore, the use of etch windows are investigated in relation to etch rate when subjected to these high pressures.  相似文献   

10.
Hybrid postprocessing etching for CMOS-compatible MEMS   总被引:2,自引:0,他引:2  
A major limitation in the fabrication of microstructures as a postCMOS (complimentary metal oxide semiconductor) process has been overcome by the development of a hybrid processing technique, which combines both an isotropic and anisotropic etch step. Using this hybrid technique, microelectromechanical structures with sizes ranging from 0.05 to ~1 mm in width and up to 6 mm in length were fabricated in CMOS technology. The mechanical robustness of the microstructures determines the limit on their dimensions. Examples of an application of this hybrid technique to produce microwave coplanar transmission lines are presented. The performance of the micromachined microwave coplanar waveguides meets the design specifications of low loss, high phase velocity, and 50 Ω characteristic impedance. Various commonly used etchants were investigated for topside maskless postmicromachining of 〈100〉 silicon wafers to obtain the microstructures. The isotropic etchant used is gas-phase xenon difluoride (XeF2), while the wet anisotropic etchants are either ethylenediamine-pyrocatechol (EDP) or tetramethylammonium hydroxide (TMAH). The advantages and disadvantages of these etchants with respect to selectivity, reproducibility, handling, and process compatibility are also described  相似文献   

11.
This study presents a bulk micromachining fabrication platform on the (100) single crystal silicon substrate. The fabrication platform has employed the concept of vertical corner compensation structure and protecting structure to integrate the wet anisotropic etching and DRIE processes. Based on the characteristics of wet anisotropic etching and DRIE, various MEMS components are demonstrated using the bulk micromachining platform. For instance, the free suspended thin film structures and inclined structures formed by the {111} crystal planes are fabricated by the wet etching. On the other hand, the mesas and cavities with arbitrary shapes and the structures with different leve l heights (or depths) are realized by the characteristics of DRIE. Since the aforementioned structures can be fabricated and integrated using the presented fabrication platform, the applications of the bulk micromachining processes will significantly increase.This research is based on the work supported by WALSIN LIHWA Corporation and the National Science Council of Taiwan under grant of NSC-91–2218-E-007–034. The authors would like to thank the Central Regional MEMS Research Center of National Science Council, Semiconductor Research Center of National Chiao Tung University and National Nano Device Laboratory for providing the fabrication facilities.  相似文献   

12.
Silicon-micromachining techniques have been combined with conventional material-synthesis methods to develop microelectrodes for 3-D microbatteries. The resulting electrodes feature an organized array of high-aspect-ratio microscale posts fabricated on the current collector to increase their surface area and volume for a given footprint area of the device. The diameter of the posts ranges from a few micrometers to a few hundred micrometers, with aspect ratios as high as 50. The fabrication approach is based on micromolding of the electrode materials and subsequent etching of the mold to release the electrode structures. Deep reactive-ion-etching or photo-assisted anodic etching has been used to form an array of deep holes in the silicon mold. Electroplating or colloidal-processing method has been used to fill the mold with battery-electrode materials. Measurements on electrochemical half-cells indicated that the 3-D electrode arrays, which are composed of vanadium oxide nanorolls or carbon, exhibited much greater energy densities (per-footprint area) than that of the traditional 2-D electrode geometries. The use of electroplating enabled us to fabricate 3-D interdigitated arrays of nickel and zinc; and battery operation was demonstrated. [2006-0293].  相似文献   

13.
As an alternative to conventional SiC reactive ion etching (RIE), polycrystalline (poly-SiC) films were patterned into micron-sized structures using sacrificial SiO2 and polycrystalline silicon (polysilicon) molds in conjunction with mechanical polishing. The molds were made from thermally grown SiO2 and LPCVD polysilicon films and were fabricated using conventional patterning techniques. The poly-SiC micromolding process combines film deposition, polishing, and selective wet chemical etching of the molds to achieve the desired pattern. The process is simple and does not suffer from the difficulties associated with RIE of SiC. Micrometer sized lines, spaces, and complex device structures have been patterned using this technique. The micromolding technique has been used in a SiC surface micromachining process to fabricate fully released lateral resonant structures  相似文献   

14.
Micromachining of diamond film for MEMS applications   总被引:1,自引:0,他引:1  
We realized two diamond microdevices: a movable diamond microgripper and a diamond probe for an atomic force microscope (AFM), consisting of a V-shaped diamond cantilever and a pyramidal diamond tip, using a microfabrication technique employing semiconductive chemical-vapor-deposited diamond thin film. The microgripper was fabricated by patterning the diamond thin film onto a sacrificial SiO 2 layer by selective deposition and releasing the movable parts by sacrificial layer etching. The diamond AFM probe was fabricated by combining selective deposition for patterning a diamond cantilever with a mold technique on an Si substrate for producing a pyramidal diamond tip. The cantilever was then released by removing the substrate. We report the initial results obtained in AFM measurements taken using the fabricated diamond probe. These results indicate that this diamond probe is capable of measuring AFM images. In addition, we have developed the anodic bonding of diamond thin film to glass using Al or Ti film as an intermediate layer for assembly. This bonding technique will allow diamond microstructures to be used in many novel applications for microelectromechanical systems  相似文献   

15.
The authors propose a new approach for fabricating an accurately vertical sidewall by deep RIE process for optical MEMS device applications. The etching area is divided in two patterns, an outline pattern and area pattern. The first pattern defines the outline of the etching area and has a uniform pattern width of 70–80 μm to achieve accurately vertical trench etching within 0.1°. The remaining area is removed by successive second etching using another pattern. The difficulties involved with multiple deep etchings are overcome by the combination of a photoresist spray coating and the side etching effect of RIE controlled by recipe control. The fabrication of mirror structure with 90.1° sidewall is demonstrated using the above procedures. Moreover, an inverted nickel mold is exhibited using electroplating. The resulting accurately vertical sidewall is considered to be effective for achieving lower insertion loss and easier optical alignment for MEMS optical devices.  相似文献   

16.
A novel etch-diffusion process is developed for fabricating high-aspect-ratio Si structures for microsensors. This is accomplished by first dry etching narrow gap Si microstructures using an electron cyclotron resonance (ECR) source, followed by a shallow B diffusion to fully convert the etched microstructures to p++ layer. Microstructures up to 40 μm deep with 2-μm-wide gaps were etched with a Cl2 plasma generated using the ECR source. Vertical profile and smooth morphology were obtained at low pressure. A shallow B diffusion at 1175°C for 5.5 h. was then carried out to convert the 40-μm-thick resonant elements to p++ layer. A second dry etching step was used to remove the thin p++ layer around the bottom of the resonant elements, followed by bonding to glass and selective wet etch. Released high-aspect-ratio Si microsensors with thicknesses of 35 μm have been demonstrated. At atmospheric pressure, only 5 Vdc driving voltage is needed for 2.5 μm vibration amplitude, which is less than the 10 Vdc required to drive 12-μm-thick resonators fabricated by conventional dissolved wafer process  相似文献   

17.
A simple low-cost technique has been developed to fabricate a mold insert for replicating polymeric tapered high aspect ratio microstructures. A backside exposure technique is used to first obtain a tapered sidewall structure as an electroplating mold in SU-8 photoresist on a glass wafer. Nickel electroplating is utilized to form the mold insert. The lowest average surface roughness of the nickel mold insert on the side that interfaces with the glass wafer during electroplating is measured to be 7.02 nm. A novel technique involving use of titanium putty is introduced here to reduce cost and effort required to fabricate the mold insert. Replication of tapered microstructures in polymeric materials utilizing the fabricated mold insert is demonstrated here in polydimethylsiloxane by a direct molding process and in polymethyl methacrylate by hot embossing. The fabrication details for the mold insert are described. Advantages and disadvantages of the use of titanium putty for achieving superior metal surface finish are given.  相似文献   

18.
We present a low cost nanofabrication method to fabricate high-aspect-ratio (HAR) polymer nanochannels using a novel silicon nanoimprint mold fabrication technique and a solvent-assisted sealing method. These nanofluidic channels are being developed for single biomolecule detection. The silicon nanoimprint mold fabrication process is based on the combination of anisotropic etching of silicon by potassium hydroxide (KOH) solution and the local oxidation of silicon (LOCOS) process. The resulting high-aspect-ratio silicon mold has smooth sidewalls owing to the anisotropic KOH etching process along the silicon crystalline geometry as well as the LOCOS process. The nanostructures in the nanoimprint molds that form the nanochannels can be easily controlled by the initial micropattern sizes defined using conventional UV lithography and the oxidation time, making this technique a practical solution for low cost and high-throughput HAR silicon nanoimprint mold fabrication. Nanoimprint molds having aspect ratios of more than 1:5.5 (width: 200 nm, height: 1.1 μm, length: 1 cm) were successfully fabricated. Nanoimprinting technique was used to create poly(methyl methacrylate) (PMMA) nanotrenches out of this nanoimprint mold. A novel solvent-assisted sealing technique was developed in order to seal the HAR PMMA nanotrenches. This technique enables the generation of nanochannels with various nanoscale dimensions without the need for complicated and expensive nanolithography tools.  相似文献   

19.
A MEMS in-line separable connector containing features for precision self-alignment is demonstrated. The concept relies on sliding connection between female and male halves to induce vertical deflections of a set of flexible conductors and establish stable electrical contacts. Electrodeposited photoresist is used to fabricate thick, nonplanar conductors, shaped by a silicon substrate that has previously been terraced by anisotropic etching. Further etched features ensure transverse and vertical self-alignment between conductor elements during mating. Prototype 10-way connectors are demonstrated with 200 /spl mu/m wide conductors on a 250-/spl mu/m pitch. Mechanical reliability of contacts during repeated mating and demating is demonstrated, and initial measurement of contact resistance reveals an encouraging value of 30 m/spl Omega/.  相似文献   

20.
 Movable microstructures are required for many applications in accelerator sensors, microvalves, micromotors, grippers and so on. With the LIGA technique, movable components can be fabricated directly by using sacrificial layer technology. This is considerably extended by the application of the LIGA technique. Normally thin metallic layers are sputtered onto an insulating substrate (e.g. silicon wafer or ceramic) and patterned by conventional photolithography and wet etching. They are used as a metalized layer and a sacrificial layer. The movable parts of the microstructures are positioned on the surface of the sacrificial layer, whereas the fixed parts are placed on the metalized area of the substrate. After stripping the resist and the sacrificial layer, the movable parts on the sacrificial layer are finished and the fixed parts remain firmly on the metalized layer. This process is rather complicated. A new technology to produce the movable parts is developed in our Lab. Firstly the normal LIGA process is used to make the sample with both metal and resist structures. The sacrificial layer pattern will be placed on the sample surface with UV lithography. A metal layer is sputtered on the sample and sacrificial layer surface as a metalized layer. By electroplating, the metalized layer will grow up to the milimeter thickness and be used as the fixed substrate. Finally removing the nonmetal substrate, resist and the sacrificial layer, the movable parts could be completed. As an example, a magnetic gripper structure is designed and fabricated by this method.  相似文献   

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