第三代数字光计算机

第三代数字光计算机第三代数字光计算机（ＤＯＣＭ）将砷化像技术工艺和全方位光互连技术结合，Ｏｐｔｉｃｏｍｐ公司正对此进行研制。这种结构利用全方位互连技术的优点：高扇入和扇出，高噪音容限，使用四维自由空间门互连。ＤＯＣ瓜将能在每秒１０“位运算的高速度下实...     

光电MCM及其物理设计的关键技术

光电多芯片组件（ＯＥＭＣＭ）以其高速、高抗扰和高组装密度等特点，在军事 大规模并行计算机方面有着广阔的应用前景。本文简要介绍光电ＭＣＭ在国内外的研究进展，光互连是实现光电ＭＣＭ的关键，与电互连相比，光互连具有功耗低、极高的带宽、互连数大、互连密度高、无接触互连，以及抗电磁干扰等优点。指出了光电ＭＣＭ物理设计的三个关键问题，散热、系统工作速度和最大光互连距离，而这些解决核心是芯片级最优分割算法的实现     

自由空间光互连系统的结构和设计分析

光互连技术是光通信网络的基础。文章结合现代微电子系统中所采用的自由空间光互连技术,进行较全面的光互连结构和设计分析     

MCM倒装焊技术在CMOS-SEED灵巧象素中的应用研究

介绍了新型ＣＭＯＳ－ＳＥＥＤ灵巧像素结构原理及相关的ＭＣＭ倒装焊混合集成技术,采用厚光致抗蚀剂作掩模,通过磁控溅射和真空蒸发相结合研究民与ＣＭＯＳ－ＥＥＤ有关的Ｉｎ凸点阵列成型,倒装焊、芯片间隙注和及子芯片衬底减薄或去除等关键工艺。     

3R光电波长变换器对WDM网中串扰的影响

具有光叉连接（ＯＸＣ）节点的波分复用（ＷＤＭ）光网络中,串扰是一个重要的限制因素。本文针对基于分送耦合开关的ＯＸＣ结构,分析了相干和非相干串扰引入的光功率恶化并进行了仿真计算。结果表明相干串扰是影响传输质量的重要因素,串扰引起的光功率恶化主要取决于复用波数Ｍ,而与输入光纤数Ｎ关系不大。如果在ＯＸＣ节点内采用３Ｒ光电波长变换器（ＯＥＷＣ）,串扰对系统的影响会降低。     

与CMOS—SEED灵巧象素相关的倒装焊工艺

介绍了新型ＣＭＯＳ－ＳＥＥＤ灵巧象素结构原理及相关的倒装焊技术。采用厚光致抗蚀剂作掩模,通过磁控溅射和真空蒸发相结合,解决了与ＣＭＯＳ－ＳＥＥＤ有关的Ｉｎ凸点阵列成型等关键工艺,并用Ｍ８－Ａ型可视对准式倒装焊系统完成了ＣＭＯＳ电路芯片和ＳＥＥＤ阵列芯片的倒装焊。     

层次化的光电多芯片组件CAD系统结构设计

为了有效地对ＯＥＭＣＭ 进行设计和封装, 在实际工作中迫切需要一种集成化的ＣＡＤ 系统。通过对ＯＥＭＣＭ 系统设计过程的研究, 提出了一种集成的层次化的ＯＥＭＣＭＣＡＤ 软件的系统结构。     

一种高性能2.0umBiCMOS工艺

本文介绍一种高性能２．０ｕｍＢｉＣＭＯＳ工艺。该工艺采用Ｐ型衬底Ｎ型Ｐ型双埋层，Ｎ型薄外延结构，掺杂多晶作为ＣＭＯＳ晶体管栅杉双极晶体管的发射极。ＣＭＯＳ晶体管源漏自对准结构，钛和铝双层金属作为元件互连和ＰＥＣＶＤ ＳｉＮｘ介质作为钝化薄膜。     

三维自由空间光互连系统光学设计

现代科学技术,特别是通信和计算机技术迫切需要高性能巨型计算机(Supercomputer).随着集成电路技术的发展,依靠提高主频来提高系统性能,难度越来越大,目前比较一致的看法认为巨型机的发展趋势是发展大规模并行处理机(Massive Parallel Machine).特别是在天基一体星间通讯用的小型化星载高速大容量并行处理计算机系统中,传统的电互连由于存在通讯瓶颈、信号延迟、封装尺寸庞大等缺点而无法满足要求.三维自由空间多处理芯片光电子集成光互连交换网络模块在大容量、超小型方面优势明显.基于此,我们采用MESH光互连网络拓扑结构,设计了一种基于MESH网络的三维自由空间光互连集成模块,对系统内部结构进行了光学设计,并提出两种解决方案.根据设计的像差要求,对其中的透镜收发阵列进行了主光线追迹计算,确定了其最终结构,并详细比较了两种方案下的成像质量,结果表明直接由透镜中心斜入射法其出射信号弥散斑为0.4630 μm,能更好地满足三维自由空间MESH光互连网络光电子集成模块的要求.(PD9)     

采用CoSi2 SALICIDE结构CMOS/SOI器件辐照特性的实验研究

讨论了ＣｏＳｉ２ＳＡＬＩＣＩＤＥ结构对ＣＭＯＳ／ＳＯＩ器件和电路抗γ射线总剂量辐照特性的影响。通过与多晶硅栅器件对比进行的大量辐照实验表明,ＣｏＳｉ２ＳＡＬＩＣＩＤＥ结构不仅可以降低ＣＭＯＳ／ＳＯＩ电路的源漏寄生串联电阻和局域互连电阻,而且对ＳＯＩ器件的抗辐照特性也有明显的改进作用。     

光电多芯片组件的自由空间光互连技术研究

自由空间光互连 (FSOI)技术使用激光在自由空间中传播 ,其表现出的特性如速度和功耗等方面较之电在连线中的传输具有的明显优点 ,从而在具有巨大发展潜力的光电多芯片组件(OE- MCM)中得到了广泛的重视。本文在建立了 OE- MCM的物理模型、逻辑模型及开销模型的基础上 ,着重对 OE- MCM中的互连分割、互连距离 (MID)最小化和 FSOI互连设计几个方面进行了研究。     

光电MCM分割算法的改进

芯片级分割技术可用于解决光电MCM(OE MCM)物理设计所面临的散热、系统速度及最大光互连距离等问题.本文给出了光电MCM分割的模型,将经改进的遗传算法(Gas)用于光电MCM的分割问题中.改进算法较标准遗传算法更适合光电MCM分割,其应用可使系统功耗降低约50%.     

基于功耗最小的光电多芯片组件优化划分算法

通过将光电MCM的功耗约束转化为光互连数最少的问题,建立了芯片级划分模型,解决了用遗传算法处理结构化设计的芯片级划分的问题,提出了基于功耗最小的光电MCM划分优化算法.实际的设计结果表明,该算法具有更强的寻优能力,比以往的算法更适合光电MCM的划分,可使系统功耗降低50%以上.     

光电多芯片模块及其在高速计算机和光通信网络中的应用

为了改善高速计算机和通信网络中的通信延迟和连通性能,从20世纪90年代初的光电子单片集成到90年代末的光电多芯片模块,人们在这一领域进行了很多研究.根据国际上近年来的相关研究报道,介绍了光电多芯片模块(OE-MCM)的结构,并阐述了其制造工艺及其在高速计算机和通信网络中的应用.     

Physical models and algorithms for optoelectronic MCM layout

Future computers will need to incorporate the parallelism of optical interconnections in order to achieve projected performance within reasonable size, power and speed constraints. This is necessary since optical interconnections have advantages in size, power, and speed over “long” distance communication. These features make optical interconnects ideal for inter-module connections in multichip module systems. Free-space optical interconnection can be one form of optical interconnections. Computer generated holograms (CGHs) are extremely attractive optical components for use in free space optical interconnections due to their ability to be computer designed. We will show that the fabrication limitations of CGHs for general interconnection networks require the need for placement algorithms for large processing element (PEs) arrays. In this paper, we will demonstrate that these fundamental CGH fabrication limitations greatly influence the computer aided design of optoelectronic interconnect networks that utilize CGHs for optical interconnections. Specifically, we show that the minimum feature size directly affects the logical placement of processing elements. Various physical models for free-space optical interconnects in parallel optoelectronic MCM systems are then identified from which we derive several logical models for analysis. We then analyze these cases and present algorithms to solve the associated layout problems. Design examples are given to illustrate the benefits of utilizing these placement algorithms in real optoelectronic interconnection networks     

光互连新进展

本文首先分析了在超大规模集成电路中电互连所遇到的困难,讨论了光学互连的优点。然后,总结了各种光互连,包括导波光互连和自由空间光互连的最近进展,最后分析了光互连研究中所遇到的困难以及相应的解决办法。     

OEMCM中光互连布局算法的研究

本文着重于具有FSOI结构的OEMCM的光学互连及其布局算法研究.针对具有CGH的FSOI系统中的互连布局特点,提出一种有效互连布局算法.运用该算法对典型的大规模互连网络示例进行的运算结果表明,该算法不仅能够有效地解决这种FSOI系统中的网络互连具有一定空间局限性的问题,而且与已有的其它互连布局算法的计算机模拟结果相比,本文的算法在布局结果、算法的收敛性等方面具有明显的优点.     

Description and evaluation of the FAST-Net smart pixel-basedoptical interconnection prototype

The design, packaging approach, and experimental evaluation of the free-space accelerator for switching terabit networks (FAST-Net) smart-pixel-based optical interconnection prototype are described. FAST-Net is a high-throughput data-switching concept that uses a reflective optical system to globally interconnect a multichip array of smart pixel devices. The three-dimensional optical system links each chip directly to every other with a dedicated bidirectional parallel data path. in the experiments, several prototype smart-pixel devices were packaged on a common multichip module (MCM) with interchip registration accuracies of 5-10 μm. The smart-pixel arrays (SPAs) consist of clusters of oxide-confined vertical-cavity surface-emitting lasers and photodetectors that are solder bump-bonded to Si integrated circuits. The optoelectronic elements are arranged within each cluster on a checkerboard pattern with 125-μm pitch. The experimental global optical interconnection module consists of a mirror and lens array that are precisely aligned to achieve the required interchip parallel connections between up to 16 SPAs. Five prototype SPAs were placed on the MCM to allow the evaluation of a variety of interchip links. Measurements verified the global link pattern across several devices on the MCM with high optical resolution and registration. No crosstalk between adjacent channels was observed after alignment. The I/O density and efficiency results suggest that a multi-terabit switch module that incorporates global optical interconnection to overcome conventional interconnection bottlenecks is feasible     

640-Gb/s high-speed ATM switching system based on 0.25-μm CMOS,MCM-C, and optical WDM interconnection

A 640-Gb/s high-speed ATM switching system that is based on the technologies of advanced MCM-C, 0.25-μm CMOS, and optical wavelength-division-multiplexing (WDM) interconnection is fabricated for future broadband backbone networks. A 40-layer, 160×114 mm ceramic MCM forms the basic ATM switch module with 80-Gb/s throughput. It consists of 8 advanced 0.25-μm CMOS LSIs and 32 I/O bipolar LSIs. The MCM has a 7-layer high-speed signal line structure having 50-Ω strip lines, high-speed signal lines, and 33 power supply layers formed using 50-μm thick ceramic layers to achieve high capacity. A uniquely structured closed-loop-type liquid cooling system for the MCM is used to cope with its high power dissipation of 230 W. A three-stage ATM switch is made using the optical WDM interconnection between high-performance MCMs. For WDM interconnection, newly developed compact 10-Gb/s, 8-WDM optical transmitter and receiver modules are used. These modules are each only 80×120×20 mm and dissipate 9.65 W and 22.5 W, respectively. They have a special chassis for cooling, which contains high-performance heat-conductive plates and micro-fans. An optical WDM router based on an arrayed waveguide router is used for mesh interconnection of boards. The optical WDM interconnect has 640-Gb/s throughput and simple interconnection     

Integrated optical interconnections

The use of optical interconnections between processors, boards, chips, and gates in electronic digital systems to overcome the current performance limitations is described. The advantages of optical interconnections in relation to the interconnection distance, the data capacity, and the interconnection functions are presented. The devices which will support practical implementation of optical interconnections and the integration of optical interconnection devices are discussed. The development of future integrated optoelectronic materials, processing, and fabrication technologies to support integrated optical electronics is also discussed