基于NoC的多核SoC片上调试构架

为解决基于NoC的多核SoC调试问题,提出一个片上硬件调试构架.详细分析了该构架的重要组成部分,调试代理及调试探测器.通过仿真验证了片上调试构架的功能,并针对逻辑综合的结果讨论了实现该调试构架的面积开销.     

可配置片上网络性能评估平台

为了弥补目前单纯采用软件或者硬件构建NoC验证平台的一些缺陷,采用软硬件结合的设计方法实现了NoC的FPGA验证与性能评估平台。利用该平台在Xilinx Virtex 6FPGA上对基于虚通道路由器的片上网络进行了验证。实验证明该验证平台功能完善,占用硬件资源少,综合时钟频率高,评估NoC系统的效率非常高。     

基于多端口存储器互连结构的多处理器系统芯片设计

多处理器系统芯片设计的关键问题之一是微处理器之间的互连结构.在总线互连结构和开关互连结构之后,提出了基于多端口存储器的第3种互连结构.利用VHDL进行了多时钟多端口存储器设计,并利用EDA工具进行了片上系统芯片的多微处理器数据通讯的功能仿真.分析了基于总线、基于开关、基于多端口存储器的3种互连结构的特点.研究表明基于多端口存储器的互连结构具有异步数据传输,数据缓冲功能;具有数据传输延时小,多微处理器系统芯片的拓扑阵列规模可扩展的优点.     

Bio-inspired fault tolerant network on chip

The integration of heterogeneous processing elements (PEs) or nodes in the System on Chip (SoC) has made the communication structure very complex. The bus based system between these components is not able to handle the communication requirements and, this has led to the idea of Network on Chip (NoC). The NoC addresses the communication requirement of different nodes on SoC. The physical sizes of devices in NoC are scaled down, including routers, processing elements and interconnects, giving rise to faults, system delay, and latency issues. Fault tolerant routing algorithms are used to recover from temporary faults while redundant resources (wires, routers) are required to overcome the permanent faults. These routing algorithms, however, still suffer from congestion problems, low bandwidth, and throughput utilization as well as lacking adaptivity and robustness. In this work, novel biologically inspired techniques were proposed for NoC using combined best effort (BE) and guaranteed throughput (GT) services. Moreover, the bio-inspired algorithms are compared and analyzed with each other using BE, GT and combined BE-GT services. The bio-inspired mechanisms of “synaptogenesis” and “sprouting” have been adopted in the proposed NoC algorithms and architecture. These techniques were implemented using the BE and GT services. With the help of these two bio-inspired techniques, the NoC becomes robust, fault tolerant and is able to efficiently utilize the throughput and bandwidth. The bio-inspired algorithms improved the accepted traffic (flit/cycle/node) by 38.99% compared to different techniques in the literature. The bio-inspired algorithm also improved the bandwidth and throughput utilization by 71.04% and 72.42% respectively compared to the XY and Odd-Even fault tolerant routing algorithms. Moreover, the bio-inspired algorithm had less end-to-end latency and interflit arrival time by 196.44% and 88.10% respectively compared to the literature techniques of XY and Odd-Even.     

基于OCP接口的片上网络性能评估平台

针对片上网络性能评估的通用性问题,提出将OCP协议运用到片上网络性能评估平台中,设计与实现了一个具有OCP接口的片上网络资源节点,该资源节点通过OCP协议与片上网络路由节点进行通信。以资源节点为主要构成单元,构建了片上网络性能评估平台。该评估平台采用集成化的设计方式,将流量产生机制、接收机制和性能分析逻辑单元集成在资源节点内部,使得平台易于灵活配置。本文结合具体的片上网络实例验证了该平台的正确性。     

片上网络中3D拓扑结构的性能评估

3D结构的片上网络(3D NoC)结合了3D集成(3D IC)和NoC技术的优势,相比2D NoC具有更为优越的性能.然而,目前大多数关于3D NoC结构的研究都集中在3D Mesh结构上.介绍了利用NIRGAM仿真器实现的另一种拓扑结构--3D Torus.在均衡负载模式和对称随机负载模式下分析评价了3D Torus网络延迟和吞吐率.结果表明,3D Torus拓扑结构的性能高于3D Mesh结构.     

Scalable architectures for real-time hyperspectral unmixing

Hyperspectral imaging instruments capture and collect hundreds of different wavelength data corresponding to the same surface. As a result, tons of information must be stored, processed and transmitted to ground. However, the downlink bandwidth is limited, and transmitting all data from the satellite to ground is a slow task that jeopardizes the use of this information for applications under real-time or near real-time constraints. This is the reason why most of the research activity is moving towards developing solutions which are able to process this data on-board, sending back to ground only relevant information.     

系统芯片总线分析模块的设计

提出了增加系统芯片观测性的一种新颖实现方法，即增加一个总线分析模块以实现对芯片的系统级监控。该总线分析模块由采样、存储、调试以及上位机接口单元组成。用户通过上位机软件可以方便地设置指令的采样点，选择自己需要的总线采样信号，对采样结果进行查询等。总线分析模块通过存储单元实现了对多次采样结果的存储。     

A new semi-flat architecture for high speed and reduced area CORDIC chip

In this contribution we present a new CORDIC architecture called ‘semi-flat’ which reduces considerably the latency time and the amount of hardware. In our semi-flat architecture the first rotations are executed with an unfolded scheme but the remaining iterations are flattened using a fast redundant addition tree. Detailed comparisons with other major contributions show that our semi-flat redundant CORDIC is 30% faster and occupy 39% less silicon area.     

Design and analysis of very high-speed network architectures

Communication architectures for very-high-speed networks are dealt with. The use of high communication speed increases the ratio between the end-to-end propagation delay and the packet transmission time. This increase restricts the utilization of the high system bandwidth in broadcast channel-based systems, causing a rapid performance deterioration. A communication system architecture characterized by the use of several parallel channels and design of the nodes' channel interface is presented. The channel-division approach is introduced, showing that for a given system bandwidth the total system capacity will be increased by bandwidth division and parallel communication. An analytic model of this system is developed, from which the proposed system's performance is obtained and performance bounds determined for multichannel slotted finite systems. The results show that the architecture has a potential to improve significantly the system performance compared to conventional single-channel-based systems. Furthermore, for a given network configuration an optimal architecture can be found which simultaneously maximizes the system throughput and minimizes the average packet delay     

未来网络体系架构研究综述

现有互联网正面临着前所未有的挑战,包括可扩展性、安全性、管控性、移动性、内容分发能力、绿色节能等一系列问题,难以通过增量式的研究模式彻底解决。在这样的背景下,创新型的未来网络体系架构研究成为当前全球关注的热点领域。通过介绍全球在该领域的研究进展情况,阐述当前该领域主要的研究成果,总结分析该领域的研究发展趋势与核心问题,期望对国内该领域的研究起到参考和帮助。     

一种基于PCI总线接口芯片的设计

PCI(Peripheral Component Interconnect)Local Bus是一种近年来在工作站和个人微机中得到广泛使用的一种局部总线规范,也是一种工业标准.研究并设计了符合PCI规范V2.2的接口芯片,着重阐述了它的功能特点、时序特征及其大致设计流程.     

基于CH368芯片的PCIE总线控制卡设计

基于CH368芯片设计了PCI Express总线接口电路,将串行传输模式转换为相对简易的并行传输模式.通过动态链接库编译和上位机软件设计,为使用CH368控制PCI Express总线提供了底层技术支持.控制卡有多通道输入及输出,可以满足数字信号、模拟信号的传输检测.     

Studies on some alternative architectures for fault-tolerantautomotive multiplexing network systems

A fault-tolerant multiplexing network architecture is described. Comparison of reliabilities and costs are made between systems without fault tolerance, systems with fault tolerance using triple modular redundancy, and systems with fault tolerance with an adaptive architecture. The relationships of these reliability and cost indexes to the system size or the number of nodes are also indicated     

基于FPGA的NoC路由节点的设计

在对NoC设计技术进行研究的基础上,建立满足要求的NoC路由节点模型,该模型采用规则的2D-Mesh拓扑结构,基于虚通道技术的虫洞数据交换方式以及无死锁的确定性XY维路由算法实现.用硬件描述语言Veril-og完成各部分的功能设计,在ModeSim仿真软件下进行功能仿真,并且在基于FPGA的NoC系统上实现了路由节点的功能.     

无线芯片域网络中PCB上的组网策略

针对无线芯片域网络(wireless chip area network,WCAN)中PCB上芯片内/间高速无线互连场景,提出了基于蜂窝Ad Hoc的组网策略,并对其网络模型、无线节点设计、多址接入、路由和流量控制策略展开研究,最后通过仿真实验与传统无线Mesh组网架构进行对比分析,得到比其更低的网络时延和抖动、更大的网络吞吐量,并在高速数据传输环境下也能保持较低的分组丢失率.验证了所提策略的优越性,对今后WCAN组网架构的研究及未来5G网络技术的发展提供了参考.     

基于CBIC的DDFS设计

通过基于标准单元CBIC设计流程,利用多级流水线技术和函数对称性算法,设计并优化了一种基于ROM结构的直接数字频率综合器（DDFS）。经VCS仿真测试和DC约束综合,该设计工作频率可达175MHz,具有面积小,功耗低等优点。能作为一个IP核,方便地集成到信号发生器、相控雷达、调频通信、声纳系统、软件无线电等领域应用。     

软件定义网络安全平台研究

SDN(软件定义网络)的安全性基于多层防御策略,它包括三种关键平台:IAM(身份和访问管理)、安全性分析、ASTRA。文章分析SDN安全平台的构成,研究包括终端用户身份安全、客户端应用标识安全和资源标识安全在内的IAM生态系统,描述安全性分析平台的基本功能、主要内容和组件构成,介绍ASTRA功能架构、深度防御策略和网络边界视图。     

接入网中V5.2接口ASIC芯片设计

V5接口提供了接入网与本地交换机间的新型开放式数字接口。重点讨论了符合V5．2接口协议的ASIC芯片的实现方案。根据该方案使用硬件描述语言（Verlog HDL)和采用自顶向下（TOP－DOWN）的设计方法实现了具体电路,并使用FPGA芯片对该电路进行了物理验证。实验表明根本本方案设计的电路正确,工作稳定可靠。