Linearization technique using bipolar transistor at 5 GHz low noise amplifier

A CMOS low noise amplifier (LNA) used in wireless communication systems, such as WLAN and CDMA, must have low noise figure, high linearity, and sufficient gain. Several techniques have been proposed to improve the linearity of CMOS LNA circuits. The proposed low noise amplifier achieves high third-order input intercept point (IIP3) using multi-gated configuration technique, by using two transistors, the first is the main CMOS transistor, and the second is bipolar transistor in TSMC 0.18 m technology. Bipolar transistor is used to cancel the third-order component from MOS transistor to fulfill high linearity operation. This work is designed and fabricated in TSMC 0.18 m CMOS process. At 5 GHz, the proposed LNA achieves a measurement results as 16 dBm of IIP3, 10.5 dB of gain, 2.1 dB of noise figure, and 8 mW of power consumption.     

Ultra low voltage, ultra low power low noise amplifier for 2 GHz applications

In this paper, a 0.29 V, 2 GHz CMOS low noise amplifier (LNA) intended for ultra low voltage and ultra low power applications is developed. The circuit is simulated in standard 0.18 μm CMOS MOSIS. A two-stage architecture is then used to simultaneously optimize the gain and noise performance. Using forward-body-biased, the proposed LNA can operate at 0.29 V supply voltage, successfully demonstrating the application potential of dynamic threshold voltage technology in the radio frequency region. The LNA provides a good gain of 26.25 dB, a noise figure of 2.202 dB, reverse isolation (S₁₂) of −59.04 dB, input return loss (S₁₁) of −122.66 dB and output return loss (S₂₂) of -11.61 dB, while consuming only 0.96mW dc power with an ultra low supply voltage of 0.29 V. To the best of authors’ knowledge this is the lowest voltage supply and the lowest power consumption CMOS LNA design reported for 2 GHz to date.     

A 1 V CMOS programmable accurate charge pump with wide output voltage range

A 1 V, programmable, accurate, high speed, single-ended charge pump is proposed, suitable for low voltage PLLs. It is designed in TSMC 90-nm digital CMOS process and it consists of four switches in a current steering configuration, a unity gain rail to rail buffer for the charge sharing effect elimination, one more rail to rail amplifier for minimizing the DC current mismatch, a programmable current bias circuitry and two drivers based on the standard cell XOR gates specific configuration for achieving good synchronization between all charge pump input pulses at the PLL lock state. Replica biasing technique is applied to all charge pump switches. Current glitches and charge mismatch are suppressed by employing a mechanism with additional switches at the output. It exhibits a maximum DC current mismatch of 1% and charge mismatch of 6% over a wide output voltage range of 0.7 V for the entire range of output currents. The wide range of the output voltage remains relatively constant and independent of the selected charge pump current amplitude. This is attained by applying appropriate variation of the W/L ratios of the bias cascode current sources via the employment of additional programmable switches such that their saturation voltages remain relatively constant, something which in turn enables the output currents range to be as wide as it is required.     

A fully integrated 2.4 GHz CMOS high power amplifier using parallel class A&B power amplifier and power-combining transformer for WiMAX application

A new structure integrated power amplifier with watt-level output power is presented in a standard 0.18 μm CMOS process for WiMAX applications. A parallel cascode class A&B power amplifier with optimized widths is proposed to increase linearity and efficiency simultaneously. A novel interleaved PCT power combiner is proposed for increasing output power that combines output current of two similar class A&B power amplifiers. Proposed interleaved transformer heightens coupling factor compared to typical transformer.