Ensembles of Neural Networks for Fault Diagnosis in Analog Circuits

A new neural network-based analog fault diagnosis strategy is introduced. Ensemble of neural networks is constructed and trained for efficient and accurate fault classification of the circuit under test (CUT). In the testing phase, the outputs of the individual ensemble members are combined to isolate the actual CUT fault. Prominent techniques for producing the ensemble are utilized, analyzed and compared. The created ensemble exhibit high classification accuracy even if the CUT has overlapping fault classes which cannot be isolated using a unitary neural network. Each neural classifier of the ensemble focuses on a particular region in the CUT measurement space. As a result, significantly better generalization performance is achieved by the ensemble as compared to any of its individual neural nets. Moreover, the selection of the proper architecture of the neural classifiers is simplified. Experimental results demonstrate the superior performance of the developed approach.     

Design of a built-in current sensor for IDDQ testing

I_DDQ testing can cover the traditional stuck-at-faults as well as other defects that may affect reliability. One of the most critical issues in I_DDQ testing is a built-in current sensor (BICS) that can be used to detect abnormal static currents. The most serious problem in the conventional current sensor is performance degradation. The purpose of this work is to present an effective BICS, which has a very small impact on the performance of the circuit under test (CUT). The proposed BICS works in two-modes, the normal mode and the test mode. In the normal mode, our BICS is totally isolated from the CUT. Thus there Is absolutely no performance degradation of the CUT. In the testing mode, our BICS detects the abnormal current caused by permanent manufacturing defects. Furthermore, the BICS requires neither an external voltage reference nor a current source. Hence, the BICS requires less area and is more efficient than the conventional current sensors. The validity and effectiveness of the proposed RIGS are verified through the HSPICE simulation and the chip test. The fabrication was done through “CMPSC8” 0.8 μm n-well process. The testing results show that our BICS operates at a speed of 25 MHz     

基于分数阶相关的模拟集成电路软故障诊断* Deng Yong(邓勇), Shi Yibing(师奕兵)and Zhang Wei(张伟)

针对模拟集成电路软故障诊断的难题,提出了基于分数阶相关的方法。首先,利用分数阶小波包将待测试电路(CUT)的Volterra级数进行分解,计算出分数阶相关函数。然后,用得到的分数阶相关函数构造出待测试电路的故障特征。通过对故障特征的比较,可以将待测试电路的各种软故障状态进行辨识并对故障实现定位。标准电路的仿真实验描述了这一方法并验证了该方法对模拟集成电路软故障诊断的有效性。     

Design of a 0.9 V 2.45 GHz Self-Testable and Reliability-Enhanced CMOS LNA

A self-testable and highly reliable low noise amplifier designed in 0.13 m CMOS technology is presented in this paper. This reliable LNA could be used to design the front-end of critical nodes in wireless local area networks to ensure data transmission. The LNA test, based on a built-in self test methodology, monitors its behavior. The test circuit is composed of one sensor and one biasing voltage sensor, and it offers high fault coverage. The high reliability is ensured by the use of redundancies. The LNA works under a 0.9 V supply voltage and the test chip has RF characteristics suitable for 802.11b/g applications. Parametric faults are injected and detected to demonstrate the efficiency of the BIST circuitry. Thanks to the switching on redundant blocks, performances are maintained and hence this proves the reliability of the methodology proposed.     

OBIST methodology incorporating modified sensitivity of pulses for active analogue filter components

In this paper, oscillation-based built-in self-test method is used to diagnose catastrophic and parametric faults in integrated circuits. Sallen–Key low pass filter and high pass filter circuits with different gains are used to investigate defects. Variation in seven parameters of operational amplifier (OP-AMP) like gain, input impedance, output impedance, slew rate, input bias current, input offset current, input offset voltage and catastrophic as well as parametric defects in components outside OP-AMP are introduced in the circuit and simulation results are analysed. Oscillator output signal is converted to pulses which are used to generate a signature of the circuit. The signature and pulse count changes with the type of fault present in the circuit under test (CUT). The change in oscillation frequency is observed for fault detection. Designer has flexibility to predefine tolerance band of cut-off frequency and range of pulses for which circuit should be accepted. The fault coverage depends upon the required tolerance band of the CUT. We propose a modification of sensitivity of parameter (pulses) to avoid test escape and enhance yield. Result shows that the method provides 100% fault coverage for catastrophic faults.     

Current monitoring circuit for fault detection in CMOS integrated circuit

This article presents a built-in current sensor (BICS), which detects faults using the current testing technique in CMOS integrated circuits. This circuit employs cross-coupled PMOS transistors, which are used as current comparators. The proposed circuit has a negligible impact on the performance of the circuit under test (CUT). In addition, no extra power dissipation and high-speed fault detection are achieved. It can be applied to deep sub-micron processes. The validity and effectiveness are verified through the HSPICE simulation on circuits with faults. The entire area of the test chip is 116×65 μm². The BICS occupies only 41×17 μm² of the area of the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix 0.35 μm 2-poly-4-metal N-well CMOS process.     

Novel Practical Built-in Current Sensors

In this paper, we propose three new built-in current sensors (BICS) topologies for on-chip IDDQ tests of analog/mixed-signal (AMS) circuits with the objective to achieve low design complexity, small area overhead and high accuracy. The first two approaches are derived from digital varicap threshold logic (VcTL) gate idea where the structure is modified for analog inputs. The third approach is a switched-cap (SC) methodology with a latch type comparator. Each design and corresponding performance results are provided in details and verified with corner and Monte Carlo analyses. All three approaches are designed as both ATE-assisted and built-in self-test (BIST) solutions. Low drop-out regulators (LDOs) in an AMS system on-chip (SOC) having more than 20 LDOs are selected as circuit under tests (CUT). The target current range is 0–100?μA to cover all LDOs. Moreover, the programmability of these proposed BICS provide a single BICS per chip solution. The overall IDDQ test time is reduced from 927?μs to 280?ns by using proposed BICS (VcTL type with PMOS capacitances). It is a significant improvement in test time and cost considering that the sensor only occupies 0.36?% of a single LDO area or equivalently 0.02?% of entire LDO subsystem.     

A Robust 130 nm-CMOS Built-In Current Sensor Dedicated to RF Applications

In this paper we present a design methodology that allows a dramatic reduction of the dependency on process variation, yielding to a new version of this BICS. Taking advantage of a 130 nm VLSI CMOS technology, the proposed BICS has a peak-to-peak dispersion lower than 10% of its output full-scale range. It makes it more suitable to implement the test functionality while maintaining the initial BICS intrinsic performances. The built-in self-test methodology is illustrated by monitoring the supply current of Low-Noise Amplifiers (LNAs). Measurements confirm the BICS’s transparency relative to the circuit-under-test (CUT) and its accuracy.

Analog Fault Diagnosis Using Conic Optimization and Ellipsoidal Classifiers

This paper introduces a new fault diagnosis strategy for analog circuits based on conic optimization and ellipsoidal classifiers. Ellipsoidal classifiers are trained for efficient and accurate fault classification of the circuit under test (CUT). In the testing phase, the output of the ellipsoidal classifiers is used to isolate the actual CUT fault. The constructed classifiers exhibit high classification rate with competitive computational complexity even if the CUT has overlapping faults. Experimental results demonstrate the superior performance of the ellipsoidal classifiers in analog fault diagnosis.     

Structural Test Approach for Embedded Analog Circuits Based on a Built-in Current Sensor

This paper presents a test method based on the analysis of the dynamic power supply current, both quiescent and transient, of the circuit under test. In an off-chip measurement, the global interconnect impedance associated with the chip package and the test equipment and, also, the chip input/output cells will complicate the extraction of the information provided by the current waveform of the circuit under test. Thus, the supply current is measured on-chip by a built-in current sensor integrated in the die itself. To avoid the effective reduction of the voltage supply, the measurement is performed in parallel by replicating the current that flows through selected branches of the analog circuit. With the aim of reducing the test equipment requirements, the built-in current sensor output generates digital level pulses whose width is related to the amplitude and duration of the circuit current transients. In this way the defective circuit is exposed by comparing the digital signature of the circuit under test with the expected one for the fault-free circuit. A fault evaluation has been carried out to check the efficiency of the proposed test method. It uses a fault model that considers catastrophic and parametric faults at transistor level. Two benchmark circuits have been fabricated to experimentally verify the defect detection by the built-in current sensor. One is an operational amplifier; the other is a structure of switched current cells that belongs to an analog-to-digital converter.     

Self-testing of fully differential multistage circuits using common-mode excitation

A fault-oriented testing of fully differential multistage circuits is investigated. The non-concurrent method is proposed, which employs the common-mode excitation of the circuit under test (CUT). Two variants of the method are considered. The first one utilizes natural inputs of each differential stage for the excitation and requires separation of stages during testing, the second one uses an extra input pin of op-amps and performs testing of multistage circuits without partitioning them into separate blocks. The contribution of this paper is the theoretical and experimental validation of the method. It is shown that the method is superior, in test quality, over the previously reported one that exploits the differential-mode excitation. The comparison is performed on the basis of test quality metrics estimated with parts per million (ppm) accuracy. To accurately calculate the test metrics: defect level, yield loss and fault coverage, a probabilistic model of performances of the CUT is derived. It is used in a probabilistic framework for evaluating the test metrics associated with manufacturing tolerances and uncertainty in a comparator threshold. The method is applied to a stagger-tuned band-pass Deliyannis–Friend filter. Work is supported by measurements in the board-level built-in self-tester (BIST) that validate the deterministic capabilities of the method and statistical experiments that validate probabilistic features.     

模拟电路故障诊断的PSpice与Matlab仿真分析研究

根据模拟电路故障诊断中的测前模拟诊断SBT法,本文采用PSpice对待测电路CUT故障进行模拟仿真,通过小波包分析和信息熵方法提取故障电路输出信号的特征向量,利用Matlab设计的神经网络算法构建故障分类器并对电路故障进行识别与诊断。仿真实验结果表明将PSpice与Matlab相结合的诊断方法能够有效地诊断模拟电路故障,为模拟电路故障诊断的教学和科研提供参考。     

Deterministic built-in test pattern generation for high-performancecircuits using twisted-ring counters

We present a new approach for built-in test pattern generation based on the reseeding of twisted-ring counters (TRCs). The proposed technique embeds a precomputed deterministic test set for the circuit under test (CUT) in a short test sequence produced by a TRC. The TRC is designed using existing circuit flip-flops and does not add to hardware overhead beyond what is required for basic scan design. The test control logic is simple, uniform for all circuits, and can be shared among multiple CUTs. Furthermore, the proposed method requires no mapping logic between the test generator circuit and the CUT; hence it imposes no additional performance penalty. Experimental results for the ISCAS benchmark circuits show that it is indeed possible to embed the entire precomputed test set in a TRC sequence using only a small number of seeds     

A BIST TPG for Low Power Dissipation and High Fault Coverage

This paper presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The proposed BIST is comprised of two TPGs: LT-RTPG and 3-weight WRBIST. Test patterns generated by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that remain undetected after LT-RTPG patterns are applied. The proposed BIST TPG does not require modification of mission logics, which can lead to performance degradation. Experimental results for ISCAS'89 benchmark circuits demonstrate that the proposed BIST can significantly reduce switching activity during BIST while achieving 100% fault coverage for all ISCAS'89 benchmark circuits. Larger reduction in switching activity is achieved in large circuits. Experimental results also show that the proposed BIST can be implemented with low area overhead.     

Method for Analog Circuit Soft-Fault Diagnosis and Parameter Identification Based on Indictor of Phase Deviation and Spectral Radius

The soft fault induced by parameter variation is one of the most challenging problems in the domain of fault diagnosis for analog circuits. A new fault location and parameter prediction approach for soft-faults diagnosis in analog circuits is presented in this paper. The proposed method extracts the original signals from the output terminals of the circuits under test (CUT) by a data acquisition board. Firstly, the phase deviation value between fault-free and faulty conditions is obtained by fitting the sampling sequence with a sine curve. Secondly, the sampling sequence is organized into a square matrix and the spectral radius of this matrix is obtained. Thirdly, the smallest error of the spectral radius and the corresponding component value are obtained through comparing the spectral radius and phase deviation value with the trend curves of them, respectively, which are calculated from the simulation data. Finally, the fault location is completed by using the smallest error, and the corresponding component value is the parameter identification result. Both simulated and experimental results show the effectiveness of the proposed approach. It is particularly suitable for the fault location and parameter identification for analog integrated circuits.     

Reducing Test Time in the High-Volume Production of Analog Circuits using Efficient Test-Vector Generation and Interpolation Techniques

Test cost is one of the main factors determining the profit margin of a device in production. Current test strategies require hundreds of measurements to determine the specifications of a parameter. In this paper, we present an automatic test-vector generation technique that is based on transfer function manipulation and requires only one circuit simulation. The proposed method consists of generating the first set of vectors by applying a derivation technique to the golden transfer function of the circuit under test (CUT). An interpolation technique allows a new transfer function to be constructed based on the first set of test vectors. The difference between the reconstructed transfer function and the golden transfer function is used to select the second set of test vectors. These new test vectors are selected to achieve the best possible fit. Our technique reduces the test vector size to values that at present can be achieved only by using powerful and time-consuming fault simulation tools. As an example, we apply the method to state variable and Chebyshev filters. We also compute the fault coverage in order to demonstrate the effectiveness of this new technique.     

基于分数阶小波的模拟电路参数估计* Deng Yong(邓勇)?, Zhang He(张禾)

Aiming at the problem of parameter estimation in analog circuits, a new approach is proposed. The approach is based on the fractional wavelet to derive the Volterra series model of the circuit under test(CUT). By the gradient search algorithm used in the Volterra model, the unknown parameters in the CUT are estimated and the Volterra model is identified. The simulations show that the parameter estimation results of the proposed method in the paper are better than those of other parameter estimation methods.     

A new BICS for CMOS operational amplifiers by using oscillation test techniques

In this paper, we present a built-in current sensor to test operational amplifiers that takes advantage of previous results where the negative supply current has been taken as the test observable using the Oscillation-test technique. The sensor is applied to a variable-length chain of OTAs considering an exhaustive analysis of catastrophic defects (opens, shorts), Gate Oxide Short and Floating Gate defects. We analyse the sensitivity of both frequency and amplitude of the current consumption. Results show that the proposed sensor provides 97% fault coverage, as the previous results suggested.     

基于扫描链结构重组的低功耗BIST方案

设计了一种改进扫描链结构的内建自测试(BIST)方案.该方案将设计测试序列发生器(TPG)中合适的n状态平滑器与扫描链的重新排序结合起来,从而达到低功耗测试且不致丢失故障覆盖率的目的.通过对15位随机序列信号的测试,发现此TPG中的n状态平滑器在降低功耗的同时还减小了故障覆盖率,遂又设计了重组扫描链的结构来解决这一问题.实验结果表明,该设计方案对于降低平均测试功耗和提高故障覆盖率都具有显著的效果.