The di/dt capability of field-controlled thyristors

Limitations to the di/dt capability of field controlled thyristors are discussed. Although the di/dt rating of these devices is not limited by plasma spreading as in conventional thyristors, destructive di/dt induced failure in surface gate devices has been observed. This failure has been shown to be due to non uniform turn-on in these devices due to inhomogeneities in the base region resistivity. Based upon this failure mechanism, it can be concluded that devices with higher di/dt ratings can be fabricated by decreasing the cathode and gate finger lengths and using thicker cathode metallization. In addition an improved device structure with vertical current flow is described with which further increases in di/dt ratings of these devices can be expected.     

Performance degradation of bidirectional triode thyristors due to di/dt stress

Performance degradation due to di/dt stress in bidirectional triode thyristors (triacs) is described. It is shown that an applied di/dt less than that required for a catastrophic failure can cause permanent damage. The breakdown voltage of the first quadrant can be degraded by a di/dt stress applied to the third quadrant, and the threshold gate trigger current for the first quadrant can be increased by a di/dt stress applied to the same quadrant. These degradations are explained by thermal damage concentrated primarily in the uppermost junctions of the thyristor.     

Chip warpage model for reliability prediction of delamination failures

A new experimental method to predict reliability for ACA type packages under temperature cycling is developed and proposed. The method introduces a new damage parameter that can be easily measured by experiment. It is proved that the linear elastic parameter, dw/dT which represents the rate of change of chip warpage with respect to temperature, efficiently reflects the common failure mechanism of ACA type packages, the interfacial delamination between the chip and the adhesive. It is demonstrated, both experimentally and numerically, that the size of delamination affects the warpage behavior of the chip. The dw/dT of the chip is monitored in real time using laser interferometers under thermal fatigue cycles up to 3000. The gradual decrease in warpage due to progressive increase in delamination is clearly emerged. As a result, a reliability curve that can predict the size of delamination and remained life is obtained. The new long-term reliability prediction method developed in this study can be applied to various advanced packages, e.g. underfilled flip–chip or TSV stacked chip packages, that embrace interfacial delamination as primary failure mode.     

Selecting an appropriate ESD protection for discrete RF power LDMOSTs

For ESD protections of RF Power MOSTs, V_t1 lowering by the RF signal - due to the dV/dt effect - can seriously degrade the RF performance. The use of a cascoded protection solves this problem. A new failure mechanism, related to the discharge of on-chip RF matching capacitors is presented. Adding a current limiting resistor in the protection solves this issue. Combining these solutions yields an appropriate protection for discrete RF power LDMOSTs.     

Evaluation of different oxidation methods for silicon for scanning capacitance microscopy

Different oxides, namely, native, thermal, and wet-chemical (H₂SO₄+H₂O₂ based) oxides on Si are evaluated in the context of scanning capacitance microscopy (SCM). The samples investigated consisted of uniformly doped Si substrates and p-type epitaxial doping-staircase structures with concentrations ranging from 5×10¹⁴ to 2×10¹⁹ cm⁻³. The bias for which the SCM signal (dC/dV) is maximised for the lowest doped region was used for comparing the different oxidation methods. It is shown that for a better evaluation of the surface oxide properties, it is essential to obtain dC/dV curves for a sufficiently large doping range. Best results in terms of low values of flat-band voltages (1 V), uniformity, and consistency across a large doping range were obtained for the wet-chemical oxide. For the native oxide case, the difference in the dC/dV peak bias values obtained at regions doped to 5×10¹⁴ to 10¹⁷ cm⁻³ was anomalously large and suggests appreciable distortion of the dC/dV curves. For the same oxidation procedure the full-width at half-maximum of the dC/dV curve obtained on the cleaved surface is typically 2 times larger than that on the planar (1 0 0) surface. It is most likely that interface states are responsible for the observed distortion.     

Wireless ATM Layouts for Chain Networks

In this paper we consider the problem of constructing ATM layouts for wireless networks in which mobile users can move along a chain of base stations. We first show that deciding the existence of a layout with maximum hop count h, load l and channel distance d is NP-complete for every fixed value of d greater or equal to 1. We then provide optimal layout constructions for the case d≤2. Finally, optimal layout constructions are obtained also for any d within the class of the so-called canonic layouts, that so far have always been shown to be the optimal ones.     

Low cycle fatigue performance of ball grid array structure Cu/Sn–3.0Ag–0.5Cu/Cu solder joints

Low cycle fatigue performance of ball grid array (BGA) structure Cu/Sn–3.0Ag–0.5Cu/Cu joints with different standoff heights (h, varying from 100 to 500 μm) and two pad diameters (d, d = 320 and 480 μm) under displacement-controlled cyclic loading was studied by experimental method and finite element (FE) simulation. A prediction method based on the plastic strain energy density and continuum damage mechanics (CDM) framework was proposed to evaluate the initiation and propagation of fatigue crack in solder joints. The results show that fatigue failure of solder joints is a process of damage accumulation and the plastic strain energy density performs a power function correlation with the cycle numbers of crack initiation and propagation. Crack propagation rate is affected by the stress triaxiality, which is dependent on the loading mode and increases dramatically with decreasing h under tensile loading, while the change of standoff height has very limited influence on the stress triaxiality under shear loading mode. Moreover, crack growth correlation constants identified in Cu/Sn–3.0Ag–0.5Cu/Cu joints with a specific geometry (h = 100 μm and d = 480 μm) can be well used to predict the fatigue life of BGA joints with other geometries. Furthermore, the results have also shown that the fatigue life of solder joints increases with decreasing the geometric ratio of h/d under the same nominal shear strain amplitude, while it drops with decreasing h/d under the same shear displacement amplitude in cyclic loading. When the geometric ratio (i.e., h/d ratio) is unchanged, the miniaturization of BGA joints brings about a decrease in fatigue life of the joints.     

A time- and temperature-dependent two-dimensional simulation of GTO turnoff process II—Inductive load case

Two-dimensional simulation was carried out for the GTO thyristor turnoff process under an inductive load with 34 A (3400 A/cm²) initial anode current and 7.2 A gate current, which is the same condition as that in which a significant current concentration into a small part of a device area was experimentally observed. A 24,000 A/cm² maximum anode current density is reached during the turnoff process in the reduced “on-region” (see text for the definition). The on-region width in the p-base reduces rapidly to 70 μm and remains at around 60 μm until the device is completely turned off. It is shown that a large amount of the stored n-base carriers in the current concentrated area are removed by the developing high electric field region in the n-base. This results in a large dV/dt current, which sustains the high current density in the current concentrated area.     

Statistical analysis of shallow p–n junction leakage increase using XTEM results probabilities

The reverse current increase for CoSi₂ silicided Si n⁺p shallow junctions is investigated, with particular interest for the diffusion component (I_d), being the fundamental lower limit. The non-uniformity of the CoSi₂ layer is shown to enhance I_d even without the presence of a catastrophic spiking defect. The n⁺ emitter thinning due to the Co reaction with Si enhances I_d by a reduction of the Gummel number. Here it is shown that, in addition, local silicide thickness variations cause a more than linear increase of I_d. A more general method for analysis of the physical variables (the average junction depth x_j and I_d) is shown, based on thickness statistical fluctuations, which are derived from cross-sectional transmission electron microscopy (XTEM) observations. It is applied for junctions with 50–200 nm mean depths.     

The field effect electron mobility of laser-annealed polycrystalline silicon MOSFETs

Measured I_d-V_d results on MOSFET's and C–V results on MOS capacitors which were fabricated on laser annealed polycrystalline silicon are presented. A scanned CW Ar⁺ laser was used to anneal the samples. Laser power varied from 10 to 15 W in increments of 1 W; beam diameter was about 40 μ m and scan rate was about 12.5 cm/s. The field effect mobility, determined from I_d-V_d measurements, increases with increasing laser power. The effects of electron trapping in the polycrystalline silicon substrate were used to explain the observed mobility of the MOSFET's. In transistors annealed at low power (< 12 W), an intercrystalline potential barrier resulting from the electron trapping at crystallite and grain boundary regions was found to be the dominant factor in the channel electron conduction. Transistors annealed at high power (≥ 12 W) have fewer defect states and the intercrystalline barrier is dominant only in the low gate voltage region. In the high gate voltage region, surface structure imperfections, which cause scattering, limit the channel conduction.     

Shallow acceptors in strained multiquantum-well Ge/Ge1−x Six heterostructures

Far infrared photoconductivity spectra due to excitation of shallow acceptors in strained multiquantum well Ge/Ge_1?x Si_x (x≈0.1) heterostuctures are investigated. It is shown that these spectra are shifted toward longer wavelengths in the far infrared region compared with those of bulk p-Ge, owing to “built-in” strain and size quantization, which lead to splitting of the light-and heavy-hole subbands in the Ge layers. Shallow acceptor spectra are calculated variationally for bulk germanium under uniaxial tension, which is “equivalent” to the strained Ge layers in the heterostructures. Although this method is only appropriate for wide quantum wells (d _Ge≈800 Å), the calculations are shown to qualitatively account for photoconductivity spectra obtained from narrower wells (d _Ge≈200 Å) as well.     

Electrical characteristics of nano-crystal Si particles for nano-floating gate memory

In these days, the researches of non-volatile memory device using nano-crystal(NC)-Si are actively progressing to replace flash memory devices. Many kinds of non-volatile memory devices such as phase-change(P)-RAM, resistance(Re)-RAM, polymer(Po)-RAM, and nano-floating gate memory(NFGM) are being studied. In this work, we study NFGM device in which information is memorized by storing electrons in silicon nanocrystal. The NFGM device has shown great promise for ultra-dense high-endurance memory device for low-power applications [S. Tiwari, et al., Appl. Phys. Lett. 68 (1996) 1377], and it is able to fabricate 1T-type device. Thus, the NFGM is considered to replace existing flash memory device. Non-volatile memory device has been fabricated by using NC-Si particles. The NC-Si particles have broad size range of 1-5 nm and an average size of 2.7 nm, which are sufficiently small to indicate the quantum effect for silicon. The memory window has been analyzed by C-V characteristic of NC-Si particles. V_d-I_d and V_g-I_d characteristics of the fabricated device have also been measured.     

Buffer structure optimization of the photoacoustic cell for trace gas detection

The equivalent four-pole network model is used to simulate one-dimension longitudinal acoustic resonator with different buffer diameters and lengths, aiming to reach a theoretic model which is able to estimate the optimal buffer geometry. In experiments, the buffer volumes are decreased gradually by filling a set of aluminum rings with different inner diameters and lengths into the buffers to get the desired dimensions. The experimental results show that the average deviation of 1.1% is obtained between the experimental results and the theoretical simulation at the buffer length of 30 mm. Experiments show that the minimum background signal occurs when the buffer length is equal to a quarter of the acoustic wavelength (λ/4). The amplitude of the photoacoustic signal is barely influenced when d _buf>3d _res. Considering that oversize of photoacoustic cell needs more measuring gas and more material, the buffer diameter can be deduced to d _buf≈3d _res. Therefore, smaller photoacoustic cell is desirable.     

Self-protection functions in direct light-triggered high-power thyristors

Direct light-triggered thyristors with integrated protection functions were fabricated and investigated. It is shown that the simultaneous integration of the light-trigger function and a reliable overvoltage self-protection can be achieved by integrating a diode into the centre of the thyristor. In addition, a dV/dt self-protection function can be integrated by a proper adjustment of the dV/dt capability of the amplifying gates and the main cathode area, ensuring a safe turn-on of the thyristor when a voltage pulse with a dV/dt value exceeding the maximum dV/dt value is applied to the device. Thyristors with different breakdown voltages ranging from 5 to 8 kV on 2-, 4- and 5-inch wafers have been realised.     

Thermal-lens and photo-acoustic methods for the determination of SiC thermal properties

In this paper we report the use of photothermal techniques such as Thermal lens (TL) spectrometry, Photoacoustic and heat capacity, ρc_p, to determine the thermo-optical parameters, such as thermal conductivity (K), thermal diffusivity (D), specific heat (c_p) and the optical path dependence with temperature (ds/dT), of an undoped polycrystalline 3C-SiC. To our knowledge, this is the first time that Thermal lens technique is used for wide band-gap systems. Results obtained for the polycrystalline sample with TL technique indicates that ds/dT is negative at room temperature. Moreover, the obtained values of thermal diffusivity and thermal conductivity are in good agreement with that found in the literature, indicating that the phototermal techniques can be used to obtain the referred parameters in circumstances where other techniques cannot be used, for example, in harsh environments.     

Two-stage hot-carrier degradation behavior of 0.18 μm 18 V n-type DEMOS and its recovery effect

Hot-carrier degradation of 18 V n-type drain-extended MOSFETs (DEMOS) is carefully investigated in this work. Two-stage degradation behavior and apparent recovery effect on the removal of the stress are observed. The first stage of the degradation is found to be mainly due to an increase of the drain series resistance (R_d), which results from the electron trapping in the drift region oxide. The degradation of R_d becomes saturated in the second stage, and the reduction of the carrier mobility in the channel begins to be dominated. In addition, recovery effect has been proved to origin from the decrease of R_d, and a new trapping-detrapping model is proposed to well describe the recovery effect in DEMOS.     

Thickness dependent dielectric breakdown of PECVD low-k carbon doped silicon dioxide dielectric thin films: modeling and experiments

The experimental results obtained on the dielectric strength E_B of carbon doped silicon dioxide thin films for various film thicknesses using I-V measurements with metal-insulator-semiconductor structures suggest a new relationship between the film thickness d and the dielectric strength E_B, i.e. E_B∝(d−d_c)⁻ⁿ. This inverse power law relationship indicates the existence of a critical thickness d_c which may correspond to an ultimate thickness limit below which the rate of detrapping of electron charges exceeds the rate of trapping and no dielectric breakdown can be observed. The newly obtained inverse power law relationship appears to be general since it is also supported by other published dielectric strength data for both amorphous and polycrystalline polymer thin films.     

Using d-limonene as the non-aromatic and non-chlorinated solvent for the fabrications of high performance polymer light-emitting diodes and field-effect transistors

Aiming to environment protection, green solvents are crucial for commercialization of solution-processed optoelectronic devices. In this work, d-limonene, a natural product, was introduced as the non-aromatic and non-chlorinated solvent for processing of polymer light-emitting diodes (PLEDs) and organic field effect transistors (OFETs). It was found that d-limonene could be a good solvent for a blue-emitting polyfluorene-based random copolymer for PLEDs and an alternating copolymer FBT-Th₄(1,4) with high hole mobility (μ_h) for OFETs. In comparisons to routine solvent-casted films of the two conjugated polymers, the resulting d-limonene-deposited films could show comparable film qualities, based on UV–vis absorption spectra and observations by atomic force microscopy (AFM). With d-limonene as the processing solvent, efficient blue PLEDs with CIE coordinates of (0.16, 0.16), maximum external quantum efficiency of 3.57%, and luminous efficiency of 3.66 cd/A, and OFETs with outstanding μ_h of 1.06 cm² (V s)⁻¹ were demonstrated. Our results suggest that d-limonene would be a promising non-aromatic and non-chlorinated solvent for solution processing of conjugated polymers and molecules for optoelectronic device applications.     

Simplified algorithm for optimum availability allocation and redundancy optimization subject to cost constraint

A simplified algorithm is described for optimum availability allocation and redundancy optimization subject to cost constraint. A series reliability structure is considered and the problems of optimum availability allocation and redundancy optimization have been tackled separately. The algorithm basically involves the evaluation of selection factor d_i for the ith sybsystem. The fixed cost increment or the redundant unit is assigned to that subsystem for which d_i is a maximum.