Bulk growth of single crystal silicon carbide

Silicon carbide (SiC) is a promising wide bandgap semiconductor material particularly suitable for future high power devices operable at high temperatures (>200 °C), at high frequencies, and in harsh environments (chemical and radiation) due to its unique physical and crystallographic properties. The absence of SiC liquid phase, under easily achievable growth conditions of pressure and temperature has created unique challenges for crystal growers.This paper reviews the basics of bulk growth processes, including source sublimation, mass transport of the Si and C species to the growing seed and crystallization. The growth process is shown to be a self-congruent phenomenon where the mass transport of the vapor species and the heat dissipation at the surface of phase transformation are interrelated. This process results in reduction of the growth velocity as a function of crystal thickness. Major mechanisms of defect generation in the grown crystal are discussed.     

Post-synthesis treatment of silicon carbide nanowires obtained in combustion synthesis

The paper describes the effects of thermal, mechanical and chemical treatment of silicon carbide nanowires (SiCNWs) obtained via combustion synthesis from Si and PTFE micropowders. The bundles of the combustion product are contaminated with various fractions of SiC and impurities like carbon, silicon and silica. Attempts have been made to debundle the wires and to remove impurities from SiCNWs samples, in order to obtain pure and shape-controlled material. The morphology of SiCNWs was examined as the material was physically and chemically modified.     

Preparation of atomically flat surfaces on silicon carbide using hydrogen etching

Hydrogen etching of 6H- and 4H-SiC(0001) surfaces is studied. The as-polished substrates contain a large number of scratches arising from the polishing process which are eliminated by hydrogen etching. Etching is carried out in a flow of hydrogen gas at atmospheric pressure and temperatures around 1600–1700°C attained on a tantalum strip heater. Post-etching atomic force microscopy images show periodic arrays of atomically flat terraces that are a few thousand angstroms wide. These terraces are separated by steps 15 Å high in the 〈1 $ < 1\bar 100 > $ 00〉 directions. Often, the surface is seen to be faceted with steps on neighboring facets forming 60° angles and offset in the c-direction by half a unit cell. Images of incompletely etched surfaces show early stages of etching where one can see remnants of surface damage in the form of arrays of hexagonal pits. On the larger scale, the surface has a hill-and-valley type morphology. The observed features are interpreted in a model based on the symmetry of the SiC unit cell and crystal miscut.     

Four-point probe characterization of 4H silicon carbide

We report on four-point probe measurements on SiC wafers as such measurements give erratic data. Current-voltage measurements on n-type SiC wafers doped to 3 × 10¹⁸ cm⁻³ are non-linear and single probe I-V measurements are symmetrical for positive and negative voltages. For comparison, similar measurements of p-type Si doped to 5 × 10¹⁴ cm⁻³ gave linear I-V, well-defined sheet resistance and the single probe I-V curves were asymmetrical indicating typical Schottky diode behavior. We believe that the reason for the non-linearity in four-point probe measurements on SiC is the high contact resistance. Calculations predict the contact resistance of SiC to be approximately 10¹² Ω which is of the order of the input resistance of the voltmeter in our four-point probe measurements. There was almost no change in two-probe I-V curves when the spacing between the probes was changed from 1 mm to 2 cm, further supporting the idea that the I-V characteristics are dominated by the contact resistance.     

Auger electron spectroscopy study of reactive ion etched silicon carbide

Reactive ion etching (RIE) of bulk 4H-SiC based on CHF₃-O₂ plasma was studied by varying the rf power and process pressure. The elements on the etched surface and the surface roughness were characterized by Auger electron spectroscopy and atomic force microscopy, respectively. It was found that the surface roughening is mainly caused by Al contamination and C rich layer (C residues) induced micromasking effect. The micromasking effect is in turn determined by the dc self-bias developed at the substrates. A threshold dc self-bias exists at around −320 to −330 V, beyond which no micromasking effect was observed. This observation is explained in terms of physical ion bombardment and sputtering in the RIE process.     

Electro-chemical mechanical polishing of silicon carbide

In an effort to improve the silicon carbide (SiC) substrate surface, a new electro-chemical mechanical polishing (ECMP) technique was developed. This work focused on the Si-terminated 4H-SiC (0001) substrates cut 8° off-axis toward 〈1120〉. Hydrogen peroxide (H₂O₂) and potassium nitrate (KNO₃) were used as the electrolytes while using colloidal silica slurry as the polishing medium for removal of the oxide. The current density during the polishing was varied from 10 μA/cm² to over 20 mA/cm². Even though a high polishing rate can be achieved using high current density, the oxidation rate and the oxide removal rate need to be properly balanced to get a smooth surface after polishing. A two-step ECMP process was developed, which allows us to separately control the anodic oxidation and removal of formed oxide. The optimum surface can be achieved by properly controlling the anodic oxidation current as well as the polishing rate. At higher current flow (>20 mA/cm²), the final surface was rough, whereas a smoother surface was obtained when the current density was in the vicinity of 1 mA/cm². The surface morphology of the as-received wafer, fine diamond slurry (0.1 μm) polished wafer, and EMCP polished wafer were studied by high-resolution atomic force microscopy (AFM).     

Temperature stability of electro-thermally and piezoelectrically actuated silicon carbide MEMS resonators

The influence of temperature between 10 °C and 100 °C on the frequency shift of electro-thermally actuated silicon carbide (SiC) clamped–clamped beams and piezoelectrically actuated SiC cantilevers has been studied. For electro-thermally actuated beams, it has been found that the rate of change of frequency varies from around ±530 ppm/°C to around ±20 ppm/°C. The differential stress of the different materials has been found to play an important role in the temperature stability of the resonators. The shifts in frequency have been shown to decrease as the temperature increases above 40 °C, attributable to the converging coefficients of thermal expansion (TCEs) of Si and SiC, resulting in reduced stress at the anchors, confirmed by simulations. Platinum, rather than aluminium, has been found to be a superior material for use as actuation electrodes because the TCEs of platinum and SiC are better matched, and converge as the temperature increases, leading to less induced stress. A larger electrode area on top of the structure can result in the thermal stress being more evenly distributed, which can improve the temperature stability, as measured with devices with a larger area of Pt electrodes as well as piezoelectrically actuated cantilevers with the electrodes covering the entire length, rather than half the length, of the cantilevers.     

Investigations on high temperature polyimide potentialities for silicon carbide power device passivation

The operation of silicon carbide (SiC) power devices under severe conditions requires the development of thermally, electrically and chemically stable package. Passivation layer provides electrical insulation and environmental protection for the SiC die. As higher junction temperature and higher electric field can be reached within SiC component, consideration must be given to the thermal stability of the dielectric properties of the material in the die surrounding. Due to their supposed high operating temperature and dielectric strength, spin coated polyimide materials appear as a possible candidate for such passivation and insulation purposes. In this paper, we study the potentialities of a high temperature polyimide from HD Microsystems, for SiC power device passivation, at temperature up to 300 °C.     

Nanoscale characterization of the silicon dioxide-silicon carbide interface using elemental mapping by energy-filtered transmission electron microscopy

Energy-filtered transmission electron microscopy (EFTEM) was used to study 6H-SiC/SiO₂ interfaces produced by thermal oxidation as a function of the oxidation conditions. Elemental maps of C and Si were used to calculate C-to-Si concentration profiles across the interfaces. Enhanced C/Si concentrations (up to ∼ 35%) were observed at distinct regions in samples oxidized at 1100°C for 4 h in a wet ambient. The data from a number of randomly selected regions indicate that re-oxidation at 950°C for 3 h significantly reduced, but did not eliminate, the amount of excess interfacial carbon.     

Electron transport properties of quantized silicon carbide inversion layers

Electron transport properties in SiC quantized inversion layers have been studied by means of a Monte Carlo procedure. It has been observed that the contribution of polar-optical phonon scattering produces a significant influence of the effective-electric field on the high longitudinal field transport regime, this being the main difference of SiC with respect to standard Si inversion layers. The energy- and momentum-relaxation times have been calculated and the results suggest that electron velocity overshoot effects are less important than in Si metal-oxide semiconductor field effect transistors. The electron mobility is not very different from their silicon counterparts, but the saturation velocity is higher.     

Normally-off trench JFET technology in 4H silicon carbide

A double gate normally-off silicon carbide (SiC) trench junction field effect transistors (JFET) design is considered. Innovative migration enhanced embedded epitaxial (ME³) growth process was developed to replace the implantation process and realize high device performance. Strong anisotropic behavior in electrical characteristics of the pn junction fabricated on (1 1 −2 0) and (1 −1 0 0) trench a-planes was observed, although quality of the pn diodes was found to be independent of trench plane orientations. Fabricated normally-off trench 4H-SiC JFET demonstrates the potential for lower specific on-resistance (R_onS) in the range of 5-10 mΩ cm² (1200 V class). A relative high T^−2.6 dependence of R_onS is observed. A breakdown voltage of 400 V in the avalanche mode was confirmed at zero gate bias conditions for cell design without edge termination. It was demonstrated that the normally-off JFETs are suitable for high temperature applications. Average temperature coefficient of threshold voltage (V_th) was calculated as −1.8 mV/°C, which is close to the MOS based Si power devices.     

The role of oxygen in electron cyclotron resonance etching of silicon carbide

The electron cyclotron resonance (ECR) etching of silicon carbide (SiC) was studied using SF₆ + O₂ based plasma. The role of O₂ was studied by varying the O₂ flow rate while keeping the total gas flow constant. It was found that oxygen enhances the etch rate at low O₂ fraction through releasing more fluorine atoms, while lowers the etch rate at high O₂ fraction by diluting fluorine atoms and forming an oxide-like layer. The etched surface roughness was found to be affected by the surface oxidation and oxygen ion related physical ion bombardment. The role of oxygen in chemical etching of carbon was found to be insignificant. In general, the etched surface is smooth and free of micromasking effect that can arise from Al contamination and C rich layer.     

Peculiarities of silicon carbide crystal growth under the diffusion mechanism of vapour transfer

In the present work the gas dynamics in the growth zone of SiC crystals is investigated. It is shown that the propagation of SiC vapour from the growth cavity walls towards the lids is effected by diffusion. On this basis the calculation of the concentration distribution of SiC vapour (n), the equilibrium vapour concentration (n_s) and the supersaturation (α = [(n – n_s)/n_s] × 100%) in the crystal growth zone at different radial and axial gradients is carried out by solving the Laplace equation in cylindrical co-ordinates for a stationary case corresponding to the conditions of crystal growth. The results obtained are compared with the available experimental data, which gives the possibility of explaining some of the observed peculiarities during SiC crystal growth from the vapour phase by the sublimation method.     

Formation of thermal decomposition cavities in physical vapor transport of silicon carbide

The relationship between seed mounting and the formation of thermal decomposition cavities in physical vapor transport grown silicon carbide was investigated. Scanning electron microscopy, energy dispersive x-ray spectroscopy, Auger electron spectroscopy, and optical microscopy were used to characterize thermal decomposition cavities at various stages of their development. The observations indicate that the attachment layer that holds the seed to the graphite crucible lid frequently contains voids. The seed locally decomposes at void locations and Si-bearing species are transported through the void. The decomposition produces a cavity in the seed; the silicon is deposited on and diffuses into the graphite lid. The formation of thermal decomposition cavities can be suppressed by the application of a diffusion barrier on the seed crystal backside.     

Controllable nanostructures on La0.7Sr0.3MnO3 thin film surfaces formed by scanning tunneling microscopy

Nanoscale structuring on La_0.7Sr_0.3MnO₃ (LSMO) thin film surfaces has been performed by scanning tunneling microscopy (STM) under ambient conditions. From line etching experiments we found that the line-depth increases in a stepwise fashion with increasing bias voltage. It also increases with decreasing scan speed and increasing scan repetition. We observed that the line-depth is an integral multiple of the LSMO out-of-plane lattice constant about 0.4 nm. Lateral structure with minimum feature size of 1 nm is possible to obtain. In addition, a four-level inverse-pyramid structure has been created on LSMO thin film surfaces. Our work shows the feasibility of using STM to fabricate controllable and complex nanostructures in LSMO thin film.     

A comparative study of micropipe decoration and counting in conductive and semi-insulating silicon carbide wafers

Micropipes are considered to be one of the most serious defects in silicon carbide (SiC) wafers affecting device yield. Developing a method to count and map micropipes accurately has been a challenging task. In this study, the different etching behavior of conductive and semi-insulating wafers in molten potassium oxide (KOH) is compared. Micropipes and closed-core screw dislocations exhibit different morphology after etching and can be easily distinguished with a polishing process. Based on a new sample preparation procedure and a digital imaging technique, a novel method of efficiently and reliably mapping and counting micropipes in both conductive and semi-insulating SiC wafers is developed.     

Ultrahigh-quality single crystals of silicon carbide by alternate repetition of growth perpendicular to c-axis

The dislocation structure of grown crystals perpendicular to c-axis was investigated by means of X-ray analysis. It was revealed that the dislocations were almost straight parallel to the growth direction in the crystals. The alternate repetition of growth in the direction to and made the dislocations and lattice distortion successfully reduced. The mechanism for the reduction was attributed to less exposure of the dislocations to a seed surface, because the straight dislocations in the seed crystal exist parallel to the seed surface. A crystal grown on {0 0 0 1} seed substrate sliced out from the crystal by the alternate repetition of growth had drastically lower defect density than conventional crystals.     

Time-dependent characteristics of titanium-silicide contacts to 6H-silicon carbide

The processing conditions necessary to achieve low resistivity of the C54-TiSi₂ phase in contact with 6H-SiC are explored. This study demonstrates that an interlayer of Si between a Ti layer and the 6H-SiC substrate suppresses the formation of TiC, and that a metallization consisting of either Ti-rich or Si-rich silicide phases may be chosen. When the Ti-to-Si layer thickness ratio is 1:3, the C54-TiSi₂ and TiSi phases are observed following a 600°C/30 min and an 850°C/30 min annealing cycle. When the Ti-to-Si layer thickness ratio is 1:1, Ti₅Si₃ and TiSi phases are observed following the same annealing cycle. Time-dependent, in-situ resistance measurements are rationalized in terms of these microstructural developments. The Ti₅Si₃/TiSi structure is demonstrated to have a resistivity of 239 μΩ·cm, whereas the TiSi₂/TiSi structure has a resistivity of only 23 μΩ·cm. Explanations for different microstructures observed are presented.     

Electrical characteristics of rectifying polycrystalline silicon/silicon carbide heterojunctions

This paper presents a study of the rectifying properties of heavily doped polycrystalline silicon (polysilicon) on 4H silicon carbide (4H-SiC). Current properties and barrier heights were found using analysis of the heterojunction. This revealed that Schottky analysis would be valid for the large barrier height devices. Isotype and an-isotype devices were fabricated on both p-type and n-type SiC and the electrical characteristics were investigated using capacitance vs voltage measurements, current vs voltage measurements (I-V), and temperature I-V measurements. Extraction of the barrier height, built-in potential, and Richardson constant were made and then compared to theoretical values for the heterojunction. Temperature I-V measurements demonstrated that the current transport mechanism is thermionic emission, confirming the validity of the Schottky diode model. The I-V characteristics show near ideal diode rectifying behavior and the capacitance-voltage characteristics show ideal junction space charge modulation for all polysilicon/SiC combinations. These experimental results match well with heterojunction band-offset estimated barrier heights and demonstrate that the barrier height of the polysilicon/4H SiC interface may be controlled by varying the polysilicon doping type.