Influence of the polymer dielectric characteristics on the performance of a quaterthiophene organic field-effect transistor

Organic field-effect transistors were fabricated with quaterthiophene as the active material and various polymeric dielectrics as the gate insulator. The conduction parameters such as mobility, threshold voltage, subthreshold swing, the maximum density of surface states etc. were found out. The performances of the devices were compared with respect to the dielectric constant, thickness and surface morphology of the gate insulator and the leakage current through the gate. Out of the three dielectrics investigated viz. parylene-C, cyanoethylpullulan and poly(methylmethacrylate); parylene-C was found to be best suited for applications in organic FETs. The online version of the original article can be found at     

Processing and performance of organic insulators as a gate layer in organic thin film transistors fabricated on polyethylene terephthalate substrate

Fabrication of organic thin film transistor (OTFT) on flexible substrates is a challenge, because of its low softening temperature, high roughness and flexible nature. Although several organic dielectrics have been used as gate insulator, it is difficult to choose one in absence of a comparative study covering processing of dielectric layer on polyethylene terephthalate (PET), characterization of dielectric property, pentacene film morphology and OTFT characterization. Here, we present the processing and performance of three organic dielectrics, poly(4-vinylphenol) (PVPh), polyvinyl alcohol (PVA) and poly(methyl methacrylate) (PMMA), as a gate layer in pentacene-based organic thin film transistor on PET substrate. We have used thermogravimetric analysis of organic dielectric solution to determine annealing temperature for spin-coated films of these dielectrics. Comparison of the leakage currents for the three dielectrics shows PVA exhibiting lowest leakage (in the voltage range of ?30 to +30 V). This is partly because solvent is completely eliminated in the case of PVA as observed by differential thermogravimetric analysis (DTGA). We propose that DTGA can be a useful tool to optimize processing of dielectric layers. From organic thin film transistor point of view, crystal structure, morphology and surface roughness of pentacene film on all the dielectric layers were studied using X-ray diffraction (XRD), atomic force microscopy (AFM) and scanning electron microscopy (SEM). We observe pyramidal pentacene on PVPh whereas commonly observed dendritic pentacene on PMMA and PVA surface. Pentacene morphology development is discussed in terms of surface roughness, surface energy and molecular nature of the dielectric layer.     

High mobility organic transistor patterned by the shadow-mask with all structure on a plastic substrate

Pentacene thin film transistors fabricated without photolithographic patterning were fabricated on the plastic substrates. Both the organic/inorganic thin films and metallic electrode were patterned by shifting the position of the shadow-mask which accompanies the substrate throughout the deposition process. By using an optically transparent zirconium oxide (ZrO₂) as a gate insulator and octadecyltrimethoxysilane (OTMS) as an organic molecule for self-assembled monolayer (SAM) to increase the adhesion between the plastic substrate and gate insulator and the mobility with surface treatment, high-performance transistor with field effect mobility 0.66 cm²/V s and I _on/I _off > 10⁵ was formed on the plastic substrate. This technique will be applicable to all structure deposited at low temperature and suitable for an easy process for flexible display.     

Study of surface-modified PVP gate dielectric in organic thin film transistors with the nano-particle silver ink source/drain electrode

We have fabricated the flexible pentacene based organic thin film transistors (OTFTs) with formulated poly[4-vinylphenol] (PVP) gate dielectrics treated by CF4/O2 plasma on poly[ethersulfones] (PES) substrate. The solution of gate dielectrics is made by adding methylated poly[melamine-co-formaldehyde] (MMF) to PVP. The PVP gate dielectric layer was cross linked at 90 degrees under UV ozone exposure. Source/drain electrodes are formed by micro contact printing (MCP) method using nano particle silver ink for the purposes of low cost and high throughput. The optimized OTFT shows the device performance with field effect mobility of the 0.88 cm2/V s, subthreshold slope of 2.2 V/decade, and on/off current ratios of 1.8 x 10(-6) at -40 V gate bias. We found that hydrophobic PVP gate dielectric surface can influence on the initial film morphologies of pentacene making dense, which is more important for high performance OTFTs than large grain size. Moreover, hydrophobic gate dielelctric surface reduces voids and -OH groups that interrupt the carrier transport in OTFTs.     

Gate Dielectrics for Organic Field‐Effect Transistors: New Opportunities for Organic Electronics

In this contribution we review the motivations for, and recent advances in, new gate dielectric materials for incorporation into organic thin‐film transistors (OTFTs) for organic electronics. After a general introduction to OTFT materials, operating principles, and processing requirements for optimizing low‐cost organic electronics, this review focuses on three classes of OTFT‐compatible dielectrics: i) inorganic (high‐k) materials; ii) polymeric materials; and iii) self‐assembled mono‐ and/multilayer materials. The principal goals in this active research area are tunable and reduced OTFT operating voltages, leading to decreased device power consumption while providing excellent dielectric/insulator properties and efficient low‐cost solution‐phase processing characteristics.     

Surface roughness and interface engineering for gate dielectrics on strained layers

The change in the morphology of various gate dielectrics (including deposited ZrO₂ and TiO₂) on strained-Si on relaxed SiGe/Si and strained-SiGe layers is studied using an atomic force microscope (AFM). The AFM observation was carried out before and after oxidation. It has been found that the oxidation rate of strained-Si was affected by the existence of the cross-hatch related surface morphology. As a result, the surface roughness increases after oxidation. The roughness increase is more pronounced in a 26% Ge-content samples than in a 9% Ge-content sample. Transmission electron microscopy (TEM) has been used to identify the structure of the deposited layers and their interface with the strained-Si or SiGe substrates. Structural and electrical characterization results for deposited high-k gate dielectrics on strained-Si using Al/ZrO₂/n-Si and Al/TiO₂/n-Si metal-insulator-semiconductor (MIS) structures with equivalent oxide thickness (EOT) of 2.5 nm are presented. Effects of nitrogen incorporation on the electrical, interfacial, charge trapping and reliability properties of ultrathin oxide/oxynitride films grown using rapid thermal oxidation on strained-SiGe substrates are also discussed.     

Thermal stability of advanced gate stacks consisting of a Ru electrode and Hf-based gate dielectrics for CMOS technology

Metallic Ru and Hf-based dielectrics such as HfO₂, HfSiO_x and HfSiON, are promising materials for the gate electrode and gate dielectrics, respectively. This paper reports on the thermal stability of gate stack systems comprised of Ru/Hf-based dielectrics. Layers of both types of material were prepared on Si substrate by metal-organic chemical vapour deposition (MOCVD). The stacks underwent exposure by rapid thermal annealing (RTA) in pure nitrogen ambience at temperatures 800, 900, and 1000 °C for 10 s. The samples were analysed using Rutherford backscattering spectrometry (RBS). Small changes were found in the stacks treated at 800 and 900 °C. The most stable stack was found to be one with a HfSiON dielectric layer, which was resistant also at temperature 900 °C. However, the annealing at 1000 °C induced massive diffusion at both interfaces for all types of stack. The results imply a limited thermal stability of the Ru/Hf-based dielectric gate stacks during the source/drain activation step.     

High-mobility solution-processed copper phthalocyanine-based organic field-effect transistors

Abstract

Solution-processed films of 1,4,8,11,15,18,22,25-octakis(hexyl) copper phthalocyanine (CuPc₆) were utilized as an active semiconducting layer in the fabrication of organic field-effect transistors (OFETs) in the bottom-gate configurations using chemical vapour deposited silicon dioxide (SiO₂) as gate dielectrics. The surface treatment of the gate dielectric with a self-assembled monolayer of octadecyltrichlorosilane (OTS) resulted in values of 4×10^?2 cm² V^?1 s^?1 and 10⁶ for saturation mobility and on/off current ratio, respectively. This improvement was accompanied by a shift in the threshold voltage from 3 V for untreated devices to -2 V for OTS treated devices. The trap density at the interface between the gate dielectric and semiconductor decreased by about one order of magnitude after the surface treatment. The transistors with the OTS treated gate dielectrics were more stable over a 30-day period in air than untreated ones.     

High-k gate oxide for silicon heterostructure MOSFET devices

Very exciting and promising results from recent developments in group-IV alloy heterostructures (viz., SiGe, SiGeC, SiC, GeC and strained-Si) have led to the belief that SiGe-based devices will open up an entirely new dimension to the future of VLSI/ULSI technology. The growth of ultrathin dielectric films on a strained group-IV alloy layer is a challenging task. As metal-oxide-semiconductor devices are being aggressively scaled down, high permittivity dielectrics are being widely investigated as alternative gate insulating layers in advanced MOS devices. The present paper reviews the recent results of different gate and high-k dielectrics on group-IV alloy layers for scaled CMOS devices, high-mobility pure-Ge channel devices and nanocrystal floating gate memories.     

Dopant enhanced in nickel silicide formation for high-<Emphasis Type="Italic">k</Emphasis> dielectric applications

The thermal stability of fully silicided NiSi with arsenic doping on silicon was investigated. The combination of full nickel silicidation gate electrodes and hafnium based high-k gate dielectrics is one of the most promising gate stacks to replace poly-Si/SiO₂/Si gate stacks in the future complementary metal–oxide–semiconductor (CMOS) sub-45 nm technology node. The aims of the work were to investigate the Ni silicide phase-related issues associated with arsenic dopant and thermal annealing on Ni–FUSI/HfO₂/Si and Ni–FUSI/HfSiO/Si gate stacks. It was found that arsenic-incorporation demonstrated some improvement in both morphology and phase stability of nickel silicided films at high processing temperatures regardless underlying gate dielectrics. The correlations of Ni–Si phase transformation and arsenic doapnt with their electrical and physical changes were established by sheet resistance measurements, X-ray diffraction (XRD), atomic force microscopy (AFM), and X-ray photoelectron spectroscopy (XPS) analysis. Furthermore, the modulation of the work function (WF) of Ni fully silicided gates by arsenic impurity is presented, comparing the effects of dopant (As) on the WF and silicide phases (NiSi and NiSi₂). It confirmed that the work function of NiSi can be tuned by implanting arsenic dopant, but it ineffective for NiSi₂ phase.     

High-mobility solution-processed copper phthalocyanine-based organic field-effect transistors

Solution-processed films of 1,4,8,11,15,18,22,25-octakis(hexyl) copper phthalocyanine (CuPc₆) were utilized as an active semiconducting layer in the fabrication of organic field-effect transistors (OFETs) in the bottom-gate configurations using chemical vapour deposited silicon dioxide (SiO₂) as gate dielectrics. The surface treatment of the gate dielectric with a self-assembled monolayer of octadecyltrichlorosilane (OTS) resulted in values of 4×10⁻² cm² V⁻¹ s⁻¹ and 10⁶ for saturation mobility and on/off current ratio, respectively. This improvement was accompanied by a shift in the threshold voltage from 3 V for untreated devices to -2 V for OTS treated devices. The trap density at the interface between the gate dielectric and semiconductor decreased by about one order of magnitude after the surface treatment. The transistors with the OTS treated gate dielectrics were more stable over a 30-day period in air than untreated ones.     

Comparison of in vivo biocompatibilities between parylene-C and polydimethylsiloxane for implantable microelectronic devices

Implantable devices are often composed of or coated with different biologically compatible materials based on their requirements. Selecting a surface material for an implantable device is not an easy task, and it is necessary to compare the biocompatibilities of the available surface materials. In this study, we perform a comparison of the in vivo biocompatibilities of polydimethylsiloxane (PDMS) and para-xylyene polymer (parylene-C) as they are considered to be candidates for a coating material for implantable microelectronic devices. For in vivo biocompatibility testing, fifty four male Sprague-Dawley rats were used for testing, and they were divided into three groups (PDMS, parylene-C and a positive control). At one, four and twelve weeks after implantation of the test object, the density of inflammatory cells and the granulation layer thickness were recorded for each group and compared with other groups using visible light and fluorescence microscopy. The thickness of the granulation layer tended to decrease over time for all of the experimental groups, whereas the granulation layer thickness remained constant in the positive control group. The thinnest capsular layer was observed for the parylene-C group and fewest inflammatory cells were observed in this group during the entire experimental period. Macrophage infiltration was minimal, even at one week, and was not observed thereafter. The parylene-C group showed better biocompatibility than the PDMS groups, both for acute and chronic implantation. Thus, parylene-C is the best candidate of the tested materials for applications involving permanent implantable micro-devices.     

Low operating voltage single ZnO nanowire field-effect transistors enabled by self-assembled organic gate nanodielectrics

The development of nanowire transistors enabled by appropriate dielectrics is of great interest for flexible electronic and display applications. In this study, nanowire field-effect transistors (NW-FETs) composed of individual ZnO nanowires are fabricated using a self-assembled superlattice (SAS) as the gate insulator. The 15-nm SAS film used in this study consists of four interlinked layer-by-layer self-assembled organic monolayers and exhibits excellent insulating properties with a large specific capacitance, 180 nF/cm2, and a low leakage current density, 1 x 10(-8) A/cm2. SAS-based ZnO NW-FETs display excellent drain current saturation at Vds = 0.5 V, a threshold voltage (Vth) of -0.4 V, a channel mobility of approximately 196 cm2/V s, an on-off current ratio of approximately 10(4), and a subthreshold slope of 400 mV/dec. For comparison, ZnO NW-FETs are also fabricated using 70-nm SiO2 as the gate insulator. Implementation of the SAS gate dielectric reduces the NW-FET operating voltage dramatically with more than 1 order of magnitude enhancement of the on-current. These results strongly indicate that SAS-based ZnO NW-FETs are promising candidates for future flexible display and logic technologies.     

Perspectives paper: First principles modeling of high-k gate dielectrics

Aggressive scaling has led to silicon dioxide (SiO₂) gate dielectrics as thin as 15 Å in state-of-the-art CMOS technologies. As a consequence, static leakage power due to direct tunneling through the gate oxide has been increasing at an exponential rate. As technology roadmaps call for sub-10 Å gate oxides within the next five years, a variety of alternative high-k materials are being investigated as possible replacements for SiO₂. The higher dielectric constants in these materials allow the use of physically thicker films, potentially reducing the tunneling current while maintaining the gate capacitance needed for scaled device operation. Recognizing that the current Si/SiO₂ system benefits from nearly 30 years of research, developing a replacement material for SiO₂ presents an immense challenge. This has prompted recent interest in novel computational approaches, such as first principles density functional theory (DFT) simulations, to computationally screen candidate dielectrics by predicting their properties based on the microscopic interactions within the system.This paper provides perspectives on the application of DFT simulations to address challenging problems of high-k gate dielectric research. We provide background and motivation for the development of high-k materials and highlight opportunities for theoretical study of such materials. We also describe specific examples of recent first principles work related to two particularly promising materials systems: silicates and aluminates.     

High dielectric constant terbium oxide (Tb2O3) dielectric deposited on strained-Si:C

High-k Tb₂O₃ films deposited on strained-Si:C and treated with different post-rapid thermal annealing temperatures were formed as alternative gate dielectrics in metal oxide semiconductor devices. The dielectrics were investigated by X-ray diffraction, X-ray photoelectron spectroscopy, atomic force microscopy, and electrical measurements. It was found that Tb₂O₃ dielectrics properly annealed at 800 °C form well-crystallized Tb₂O₃ structures with few defects.     

Integrated metal-Langmuir-semiconductor field effect transistors

An array of integrated, n-channel, enhancement mode, field effect transitors using Langmuir-Blodgett films as gate insulators have been fabricated and studied.

Effective insulator charge densities for the metal-Langmuir-semiconductor field effect transistors (MLSFETs) were found to be on the order of 10¹¹ q cm^-2. The surface mobility of the MLSFETs was found to be between 550 and 600 cm² V^-1 s^-1 at effective fields of 5 × 10⁷ V m^-1. The mobility was also found to be independent of the effective insulator charge density. These mobility figures compare quite favorably with the published figures for Si-SiO₂ devices with similar effective charge densities and fields.

Stability of the MLSFETs was studied and found to be good; unencapsulated storage for several days to a week at room temperature and humidity levels produced no discernable difference in the I-V characteristics.

The characteristics of the devices are shown to be accurately modeled using the traditional MOSFET model and equations. Saturated transconductance vs. the gate width-to-length ratio and gate bias plots were linear, indicating that the device would be useful as a replacement for a similar MOSFET.     

N-channel thin-film transistors based on 1,4,5,8-naphthalene tetracarboxylic dianhydride with ultrathin polymer gate buffer layer

N-channel operation of thin-film transistors based on 1,4,5,8-naphthalene tetracarboxylic dianhydride (NTCDA) with a 9-nm-thick poly(methyl methacrylate) (PMMA) gate buffer layer was examined. The uniform coverage of the ultrathin PMMA layer on an SiO₂ gate insulator, verified by X-ray reflectivity measurement, caused the increase of electron field-effect mobility because of the suppression of electron traps existing on the SiO₂ surface. In addition, air stability for n-channel operation of the NTCDA transistor was also improved by the PMMA layer which possibly prevented the adsorption of ambient water molecules onto the SiO₂ surface.     

Human fibroblast attachment on fibrous parylene-C thin-film substrates

Although the polymeric form of parylene-C is used in many medical devices, the mechanistic nature of cellular attachment to polymeric parylene-C is not clear. We examined the effects of (i) substrate morphology, (ii) surface wettability and (iii) presence of serum proteins on fibroblast attachment. A physicochemical vapor deposition technique was implemented to deposit flat parylene-C substrates as well as fibrous substrates of three different morphologies: slanted columnar, chevronic and chiral. Flat parylene-C surfaces were moderately hydrophobic while fibrous substrates were superhydrophobic. Pretreatment with oxygen plasma changed the substrate surfaces from hydrophobic to superhydrophilic. The attachment efficiency of human fibroblast cells to the flat and three fibrous thin-film parylene-C substrates was investigated. Fibroblast attachment was better on fibrous substrates than on flat substrates, and oxygen plasma pretreatment facilitated fibroblast attachment on all four morphologies. Serum proteins also facilitated cell attachment on all substrates. The combination of oxygen plasma pre-treatment and serum proteins increased fibroblast adhesion in an additive manner on flat, but not on fibrous parylene-C substrates. The morphology of cell–substrate interactions differed between fibrous and flat parylene-C substrates.     

A Monolayer MoS2 FET with an EOT of 1.1 nm Achieved by the Direct Formation of a High-κ Er2O3 Insulator Through Thermal Evaporation

Achieving the direct growth of an ultrathin gate insulator with high uniformity and high quality on monolayer transition metal dichalcogenides (TMDCs) remains a challenge due to the chemically inert surface of TMDCs. Although the main solution for this challenge is utilizing buffer layers before oxide is deposited on the atomic layer, this method drastically degrades the total capacitance of the gate stack. In this work, we constructed a novel direct high-κ Er₂O₃ deposition system based on thermal evaporation in a differential-pressure-type chamber. A uniform Er₂O₃ layer with an equivalent oxide thickness of 1.1 nm was achieved as the gate insulator for top-gated MoS₂ field-effect transistors (FETs). The top gate Er₂O₃ insulator without the buffer layer on MoS₂ exhibited a high dielectric constant that reached 18.0, which is comparable to that of bulk Er₂O₃ and is the highest among thin insulators (< 10 nm) on TMDCs to date. Furthermore, the Er₂O₃/MoS₂ interface (D_it ≈ 6 × 10¹¹ cm⁻² eV⁻¹) is confirmed to be clean and is comparable with that of the h-BN/MoS₂ heterostructure. These results prove that high-quality dielectric properties with retained interface quality can be achieved by this novel deposition technique, facilitating the future development of 2D electronics.